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1、Chapter 10 Memory Interface,Instructor：Dr. Alex Yu,Contents,Memory Devices Address Decoding 8086 Memory Interface Keynotes: Address Decoding,2019/6/28,第2页,Memory Devices,Type ROM: Read-only memory RAM: Read-Write memory Four commonly used memories ROM Flash, EEPROM Static RAM (SRAM) Dynamic RAM (DRA
2、M), SDRAM, RAMBUS, DDR RAM Generic pin configuration,2019/6/28,第3页,Memory Chip,Address Pins The number of address pins is related to the number of memory locations 1M for 20 pins Data Pins The data pins are typically bi-directional in read-write memories. The number of data pins is related to the si
3、ze of the memory location. For example, an 8-bit wide (byte-wide) memory device has 8 data pins. Catalog listing of 1K X 8 indicate a byte addressable 8K bit memory with 10 address pins. Control Pins #CS or #S: Chip Select, enable read/write operations #OE or #G: Output Enable, enables/disables a se
4、t of tri-state buffers #WE: write enable Some chips, R/#W,2019/6/28,第4页,ROM,Non-volatile memory: Maintains its state when powered down. There are several forms: ROM: Factory programmed, cannot be changed. Older style. PROM: Programmable Read-Only Memory. Field programmable but only once. Older style
5、. EPROM: Erasable Programmable Read-Only Memory. Reprogramming requires up to 20 minutes of high-intensity UV light exposure. Flash, EEPROM: Electrically Erasable Programmable ROM. Also called EAROM (Electrically Alterable ROM) and NOVRAM (NOn-Volatile RAM). Writing is much slower than a normal RAM.
6、 Used to store setup information, e.g. video card, on computer systems. Can be used to replace EPROM for BIOS memory.,2019/6/28,第5页,ROM,Address Bus Data Bus Control Bus Chip Enable: #CE Output Enable: #OE,2019/6/28,第6页,Read Operation,2019/6/28,第7页,Standard EPROM ICs,2019/6/28,第8页,Intel 2716 EPROM,20
7、19/6/28,第9页,Intel 2716 EPROM,2019/6/28,第10页,RAM,2019/6/28,第11页,RAM,DRAM vs SRAM SRAMs are limited in size. DRAMs are available in much larger sizes, e.g., 64M1. DRAMs MUST be refreshed (rewritten) every 2 to 4 ms Since they store their value on an integrated capacitor that loses charge over time. Th
8、is refresh is performed by a special circuit in the DRAM which refreshes the entire memory. Refresh also occurs on a normal read or write. The large storage capacity of DRAMs make it impractical to add the required number of address pins. Instead, the address pins are multiplexed.,2019/6/28,第12页,RAM
9、,2019/6/28,第13页,TI 4016 SRAM,2019/6/28,第14页,DRAM,The TMS4464 can store a total of 256K bits of data. It has 64K addressable locations which means it needs 16 address inputs, but it has only 8. The row address (A0 through A7) are placed on the address pins and strobed into a set of internal latches.
10、The column address (A8 through A15) is then strobed in using CAS.,2019/6/28,第15页,DRAM Timing,2019/6/28,第16页,Address Decoding,The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the ad
11、dress space of the processor, decoding is necessary. For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. A decoder can be used to decode the additional 9 address pins and allow the EPR
12、OM to be placed in any 2KB section of the 1MB address space.,2019/6/28,第17页,Address Decoding,2019/6/28,第18页,To determine the address range that a device is mapped into: This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H). NAND gate decoders are not often used Large fan-in
13、NAND gates are not efficient Multiple NAND gate ICs might be required to perform such decoding Rather the 3-to-8 Line Decoder (74LS138) is more common.,Address Decoding,2019/6/28,第19页,3-8 Line Decoder 74LS138,Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, resp
14、ectively. Each output of the decoder can be attached to an 2764 EPROM (8K8).,2019/6/28,第20页,Decoding with 74LS138,2019/6/28,第21页,8088/80188 (8-bit) Memory Interface,The memory systems sees the 8088 as a device with: 20 address connections (A19 to A0). 8 data bus connections (AD7 to AD0). 3 control s
15、ignals, IO/M, RD, and WR. Well look at interfacing the 8088 with: 32K of EPROM (at addresses F8000H through FFFFFH). 512K of SRAM (at addresses 00000H through 7FFFFH). The EPROM interface uses a 74LS138 (3-to-8 line decoder) plus 8 2732 (4K8) EPROMs.,2019/6/28,第22页,8088/80188 (8-bit) Memory Interfac
16、e,2019/6/28,第23页,8088/80188 (8-bit) Memory Interface,2019/6/28,第24页,8086 - 80386SX 16-bit Memory Interface,2019/6/28,第25页,8086 - 80386SX 16-bit Memory Interface,2019/6/28,第26页,8086 - 80386SX 16-bit Memory Interface,2019/6/28,第27页,Memory Interface,2019/6/28,第28页,Hardware Organization of the Memory Address Space,2019/6/28,第29页,Data Transfer,8088,2019/6/28,第30页,Data Transfer,8086,2019/6/28,第31页,Data Transfer,8086,2019/6/28,第32页,Data Transfer,8086,2019/6/28,第33页,Data Transfer,8
