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1、6.7用VHDL语言描述时序逻辑电路,6.7.1移位寄存器的VHDL描述,4位双向移位寄存器74LS194的VHDL描述,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HC194 IS PORT(D :IN STD_LOGIC_VECTOR(0 TO 3); CR,SR,SL,S1,S0:IN STD_LOGIC; CP:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(0 TO 3); END HC194; ARCHITECTURE ONE OF HC194 IS SIGNAL PCX:STD_LOGIC_VECT
2、OR(0 TO 3); BEGIN,PROCESS(CR,CP) BEGIN IF(CR=0) THEN PCX=“0000“; ELSE IF(cp EVENT)AND(CP=1) THEN IF(s1=0) AND (s0=1) THEN PCX(0)=SR; PCX(1)=PCX(0); PCX(2)=PCX(1); PCX(3)=PCX(2); ELSIF (s1=1) AND (s0=0) THEN PCX(0)=PCX(1); PCX(1)=PCX(2); PCX(2)=PCX(3); PCX(3)=SL;,ELSIF (s1=1) AND (s0=1) THEN pcx(0)=d
3、(0); pcx(1)=d(1); pcx(2)=d(2); pcx(3)=d(3); ELSE null; END IF; END IF; END IF; END PROCESS; Q=PCX; END ONE;,6.7.2计数器的VHDL描述,8421BCD码十进制计数器的VHDL描述,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT10 IS PORT(CP:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COUNT10; ARCHITECTURE ONE OF COUNT10 IS SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);,6.7.2计数器的VHDL描述,8421BCD码十进制计数器的VHDL描述,BEGIN PROCESS(CP) BEGIN IF CP EVENT AND CP=1 THEN IF COUNT=”1001” THEN COUNT=”0000”; ELSE COUNT=COUNT+1; END IF; END IF; END PROCESS ; Q=COUNT; END ONE;,
