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1、W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 - Preliminary - Revision B 8M-BIT, 16M-BIT AND 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI 元器件交易网w w w . c e c b 2 b . c o m W25Q80, W25Q16, W25Q32 - 2 - Table of Contents 1. GENERAL DESCRIPTION . 5 2. FEATURES. 5 3. PIN
2、CONFIGURATION SOIC 208-MIL. 6 4. PAD CONFIGURATION WSON 6X5-MM 6 5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM 6 6. PIN CONFIGURATION SOIC 300-MIL. 7 7. PIN DESCRIPTION SOIC 300-MIL 7 7.1 Package Types.8 7.2 Chip Select (/CS) 8 7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
3、 8 7.4 Write Protect (/WP). 8 7.5 HOLD (/HOLD) . 8 7.6 Serial Clock (CLK) 8 8. BLOCK DIAGRAM 9 9. FUNCTIONAL DESCRIPTION . 10 9.1 SPI OPERATIONS .10 9.1.1 Standard SPI Instructions.10 9.1.2 Dual SPI Instructions10 9.1.3 Quad SPI Instructions.10 9.1.4 Hold Function .10 9.2 WRITE PROTECTION11 9.2.1 Wr
4、ite Protect Features11 10. CONTROL AND STATUS REGISTERS. 12 10.1 STATUS REGISTER 12 10.1.1 BUSY12 10.1.2 Write Enable Latch (WEL)12 10.1.3 Block Protect Bits (BP2, BP1, BP0)12 10.1.4 Top/Bottom Block Protect (TB).12 10.1.5 Sector/Block Protect (SEC)12 10.1.6 Status Register Protect (SRP1, SRP0).13 1
5、0.1.7 Quad Enable (QE)13 10.1.8 Status Register Memory Protection15 10.2 INSTRUCTIONS.18 10.2.1 Manufacturer and Device Identification 18 10.2.2 Instruction Set Table 119 10.2.3 Instruction Set Table 2 (Read Instructions) 20 元器件交易网w w w . c e c b 2 b . c o m W25Q80, W25Q16, W25Q32 Publication Releas
6、e Date: September 26, 2007 - 3 - Preliminary - Revision B 10.2.4 Write Enable (06h)21 10.2.5 Write Disable (04h).21 10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h).22 10.2.7 Write Status Register (01h) 23 10.2.8 Read Data (03h).24 10.2.9 Fast Read (0Bh).25 10.2.10 Fast Read Dual
7、 Output (3Bh).26 10.2.11 Fast Read Quad Output (6Bh)27 10.2.12 Fast Read Dual I/O (BBh).28 10.2.13 Fast Read Quad I/O (EBh).30 10.2.14 Page Program (02h).32 10.2.15 Quad Input Page Program (32h) 33 10.2.16 Sector Erase (20h) .34 10.2.17 32KB Block Erase (52h).35 10.2.18 64KB Block Erase (D8h).36 10.
8、2.19 Chip Erase (C7h / 60h).37 10.2.20 Erase Suspend (75h)38 10.2.21 Erase Resume (7Ah)38 10.2.22 Power-down (B9h)39 10.2.23 High Performance Mode (A3h).40 10.2.24 Release Power-down or High Performance Mode / Device ID (ABh).40 10.2.25 Read Manufacturer / Device ID (90h).42 10.2.26 Read Unique ID N
9、umber 43 10.2.27 JEDEC ID (9Fh) .44 10.2.28 Mode Bit Reset (FFh or FFFFh) .45 11. ELECTRICAL CHARACTERISTICS (PRELIMINARY). 46 11.1 Absolute Maximum Ratings46 11.2 Operating Ranges. 46 11.3 Endurance and Data Retention 47 11.4 Power-up Timing and Write Inhibit Threshold 47 11.5 DC Electrical Charact
10、eristics 48 11.6 AC Measurement Conditions 49 11.7 AC Electrical Characteristics 50 11.8 AC Electrical Characteristics (contd). 51 11.9 Serial Output Timing.52 11.10 Input Timing.52 11.11 Hold Timing .52 12. PACKAGE SPECIFICATION53 元器件交易网w w w . c e c b 2 b . c o m W25Q80, W25Q16, W25Q32 - 4 - 12.1
11、8-Pin SOIC 208-mil (Package Code SS) 53 12.2 8-Pin PDIP 300-mil (Package Code DA) 54 12.3 8-contact 6x5 WSON (Package Code ZP). 55 12.4 8-contact 6x5 WSON Contd. . 56 12.5 16-Pin SOIC 300-mil (Package Code SF) 57 13. ORDERING INFORMATION 58 13.1 Valid Part Numbers and Top Side Marking 59 14. REVISIO
12、N HISTORY 60 元器件交易网w w w . c e c b 2 b . c o m W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 5 - Preliminary - Revision B 1. GENERAL DESCRIPTION The W25Q80 (8M-bit), W25Q16 (16M-bit), and W25Q32 (32M-bit) Serial Flash memories provide a storage solution for systems with limit
13、ed space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power suppl
14、y with current consumption as low as 5mA active and 1A for power-down. All devices are offered in space-saving packages. The W25Q80/16/32 array is organized into 4,096/8,192/16,384 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instructions.
15、Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80/16/32 has 256/512/1024 erasable sectors and 16/32/64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in
16、 applications that require data and parameter storage. (See figure 2.) The W25Q80/16/32 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI using SPI pins: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output
