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1、第三章 门电路,Chapter 3 Logic Gates,本章任务,1.学习各种门电路的逻辑功能； 2.学习各种CMOS门电路的组成， 会分析逻辑门电路的逻辑结构， 及等效的逻辑关系； 3.学习CMOS、TTL逻辑门的输入输出 特性及接口电路； 4.,概述,门电路的分类： 按门电路的结构分类: .CMOS . TTL .ECL 按门电路的规模分类: .SSI .MSI .LSI .VLSI（PLD =） .ASIC,3.按门电路的逻辑功能分类:,1. 2. 3. 4. 5. 6.D 7. 8.ri-state 9.CMOS Transmission gate,MOSFET的结构和原理,沟道增
2、强型MOS管结构示意图及增强型MOS的符号,返回,图1.4.8 uDS 0时uGS对导电沟道的影响,uGS为大于UGS(th)的某一值时uDS对iD的影响,返回,N沟道增强型MOS管的特性曲线,返回,UO,Rd,Ed,EGS,N沟道增强型MOS管反相器,1.Logic level for CMOS Logic circuits,5.0v 3.5v 1.5v 0v,Sec2.1 CMOS Inverter,MOS Transistor as a voltage-controlled resistance,N-MOS P-MOS,+G,- S,D,- G,S,- D,+,+,S,G,D,S,G,D
3、,G (U in),S,D,R,+G,- S,D,UDS,-,+,UGS,+,-,UDD,RD,-,+,UGS,Vout,Vin,0,关 门,开 门,v,+5v,3.5v,1.5v,2.CMOS inverter NMOS inverter,UDS,(UGS),CMOS inverter（p-Channel as Load),Vin,Vout,VDD=+5v,N-Channel,p-Channel,Q2,Q1,0.0v,5.0v,Vout,Vin,0,关 门,开 门,v,+5v,3.5v,1.5v,3.5V 1.5V,CMOS inverter,Sec 3.2 CMOS Logic Gate,
4、1. NAND gate 2.CMOS NOR gate 3.CMOS NONINVERTING BUFFER 4.AND-OR-NOT gate 5.OD. 6.EX-OR gate . 7.Three-state gates-1 8.CMOS Transmission gate,1.CMOS NAND gate,NAND gate 的逻辑功能,A B,0 0 0 1 0 1 1,T1 T2 T3 T4,On on off off Off on on off On off off on Off off on on,f,1 1 1 0,NAND gate 的电路结构,CMOS NAND gat
5、e 的电路符号,&,2.CMOS NOR gate,NOR gate 的逻辑功能,A B,0 0 0 1 0 1 1,T1 T2 T3 T4,On on off off On off off on Off on on off Off off on on,f,1 0 0 0,NOR gate 的电路结构,CMOS NOR gate 的电路符号,1,4.3-input NAND gate; 3. 2-input AND gate,5.CMOS NONINVERTING BUFFER,OR-AND-NOT gate,6.AND-OR-NOT gate,p,p,N,N,p,p,N,N,Q,F,A B
6、C D,F,A B C D,AND-OR-NOT gate 的逻辑功能,A B C D,0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1,T1 T2 T3 T4,Off on off on On on Off on on off On On On off off on on on On off on off On off on off On off on off On off on off,f,1 1 1 0,T5 T6 T7 T8,Off on off on Off on on of
7、f On off off on On off on off,Off on off on Off on on off On off off on On off on off,Off off on on Off on on off On off off on On off on off,Off off on on Off on on off On off off on On off on off,1 1 1 0,1 1 1 0,0 0 0 1,6.AND-OR-NOT gate另一种结构,A B,C D,VDD,f,T1,T3,T5,T7,T2,T4,T6,T8,Sec3.3.异或门及其它门 (E
8、x-OR and Other Gates),1. 异或门及其应用 (Ex-OR Gates & its Applications) 2.传输门及其应用 (Transmission Gates & Applications) 3.三态门(Tri-state Gate ) 4.漏极开路门(OD-Gat) 5.线与逻辑(Wiring “AND” Logic),1.EX-OR gate,F=AB+AB,=1,p,(1).电路结构,T7,T8,T9,T10,T5,T6,T4,T3,T2,T1,(2).异或门的性质及可编程性,电路符号,0 0 0 0 1 1 1 0 1 1 1 0,En,D,F,=1,D
9、,En,F,D,En,F,A B,A B,A,B,可编程 同相门,可编程 反相门,(3).异或门应用 .可编程（ Be controlled ） XOR/ X-NOR,Lecture:p.86,A,B,CONTROL(LOW / HIGH),F=ABC =C (AB) + C (AB),1,2,AB,C,F,0,1,AB,(AB),F,(3). 异或门应用举例 奇偶校验功,AB,F2=ABC,A,B,C,Controlled,.Use the even-parity generator below figure to generate the even-parity bit for 11011
10、101.,Application Example 3:,Even/Odd-parity generator Application Example 4:,Q=1时，A0A6Odd1 . Control=0， parity bit=1； . Control=1， parity bit=0； Q=0时，A0A6even 1 . Control=0， parity bit=0； . Control=1， parity bit=1；,Q,Parity checker,A7A0=EVEN1 Out=0 A7A0=Odd 1 Out=1,Out,74Ls280 9-bit generator/checke
11、r,0,0,1,0,0,1,1,1,Comparator Application Example 5:,B3A3 B2A2 B1A1 B0A0,Y,1,4位等值比较器：当B3=A3, B2=A2, B1=A1, B0=A0 时，A等于B. 输出Y=1.,Y,Application-a phase detector circuit using an xoR and XNOR Application Example 7: Lecture-p.87,What will be the x and y outputs from the circuit in below figure, if the A
12、and B inputs are either out-of- phase or in phase?,波形输入分析： 下一页,A B A B A B,画鉴相器输出波形,异或门应用 Ex-OR example:,设计一个电路，能够实现将4位格雷码G1G2G3G4转换成4位二进制码D1D2D3D4.的功能。,使用XOR门实现数码转换电路， 设计方法可以有几种,用卡诺图化简方法可以采用 最小项积之和（NAND门）方法； 也可采用和之积的方法（即NOR门）实现； 第三种方法采用直接观察法（XOR实现）； 第四种方法，采用XOR/NXOR 门实现的方法。 引出卡诺图对角邻与偏邻化简法。介绍单变量、双变量
13、和多个变量的卡诺图对角邻与偏邻化简法。,Gray code To Binary code,Gray codeBinary code,D1,D2,G1G2,G3G4,00 01 11 10,G3G4,G1G2,00 01 11 10,00 01 11 10,00 01 11 10,00 01 11 10,G3G4,G1,G1G2,G1G2,Gray code Binary code,D3,D4,G1G2,G3G4,00 01 11 10,G3G4,G1G2,G3G4,00 01 11 10,00 01 11 10,00 01 11 10,G1G2G3,G1G2G3,G1G2G3,G1G2G3,G
14、1G2G3G4,4位格雷码转换成二进制码的电路 (Gray code conversion binary algorithm implementation),2.CMOS Transmission gate,En A,B,Two-input multiplexer using CMOS transmission gate,P-MOS,N-MOS,分析：,3.With Buffer-AND-NOT gate,A B,Y,A B,Y=(AB),(A+B)=(AB),4.Three-state gates-1,Y,B,C,D,Tri-state output gates -2,CMOS TRI-STATE gate-3,With NOR gate control,With NAND gate control,A En,f,En A,F,CMOS Tri-state gate-4,Tri-state gates new symbols,Tri-state application,BUS,En1,En2,Eni,Data1,Data2,Data-i,4000系列,74xx240 74HC240,74LS126,Tri-state gate old symbol,En,En,En,En,Sec.
