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1、陳慶瀚 機器智慧與自動化技術(MIAT)實驗室 國立中央大學資工系 2009年10月8日,ESD-04 VHDL硬體描述語言概論 VHDL Hardware Description Language,2,History of VHDL, 1980年代初：VHSIC（Very High Speed Integrated Circuit）的計劃以gate level的方式描述電路。 1982年：VHSIC硬體描述語言(VHSIC Hardware Description Language），簡稱VHDL。 1987年： VHDL成為IEEE標準(IEEE 1076) 。 1988年：美國國防部規定
2、所有官方的ASIC設計均要以VHDL為其硬體描述語言，自此之後VHDL也漸漸成為業界間流通的一種標準。 1994 ： IEEE發表新版 VHDL Standard 1164 1996 ：結合電路合成的程式標準規格，發表IEEE 1164.3 現在：VHDL已經成為電子設計自動化（EDA）工程的共通語言； 未來：朝向系統階層(system-level)的設計,3,Introduction to VHDL,Structure Model VHDL code Entity Architecture Component Configuration,4,Top-down IC Design Flow,5
3、,VHDL Design Flow,6,Timing Delay,Ideal delay time = 0 for functional level Real delay time delay factors : technology ( TTL, CMOS, GaAs ) RC delay fan-out,7,Simulating Strategy,Time driven Monitor value at every time period High precision SPICE, etc,Event driven Record when value change (event ) Les
4、s simulation time and memory Behavior simulator : VHDL, Verilog,8,Concurrent and Sequential,Concurrent Each statement execute at the same time ( logic circuits ) Sequential Statements execute in series ( programming languages as C, FORTAN ),Statement A = B; B = C; assume : A=1,B=2,C=3 concurrent res
5、ult A = B = C= 3 sequential result A = B = 2 B = C = 3,9,Synchronous and Asynchronous,同步的基準通常指CLOCK Synchronous signal change value when clock assert.,10,Logic Values and Multi-driven,9 value of IEEE std 1164 -1993 : type STD_LOGIC is ( U - Uninitialized X - Forcing Unknown 0 - Forcing Low 1 - Forci
6、ng High Z - High Impedance W - Weak Unknown L - Weak Low H - Weak High - - Dont Care );,Multi-driven problem wire and wire or,11,HDL Design Modeling,Structure description of COMPONENT and WIRE Data-Flow concurrent signal assignment (select, conditional ) Behavior Sequential signal assignment (high l
7、evel language) Mix of above three,12,Traditional Design,IF (control = 1 ) THEN z = input; ELSE z = NOT ( input ); ENDIF;,規格(SPEC) : 當control=1時, z = input 否則 z = inv(input),13,Entity,描述 I/O port 的規格 語法:,Example: D Flip-Flop,ENTITY entity_name IS PORT ( ); END entity_name ;,ENTITY dff IS PORT(D :IN S
8、TD_LOGIC; CK :IN STD_LOGIC; CLR:IN STD_LOGIC; Q :OUT STD_LOGIC; Qb :OUT STD_LOGIC); END dff; - This is a comment,14,Architecture,描述內部電路 一個 Entity 可存在多個Architecture 語法:,ARCHITECTURE a_name OF e_name IS - signals,variables declaration BEGIN - statements END a_name ;,15,Architecture - Example : dff,ARC
9、HITECTURE behavior OF dff IS BEGIN PROCESS BEGING IF(CLR = 1) THEN Q = 0; ELSE CKEVENT AND CK=1 THEN Q = D; ENDIF; WAIT ON CLR, CK; END PROCESS; END behavior;,16,Component,宣告元件(logic gate)的名稱與 I/O port 語法:,Example: nand2,COMPONENT comp_name PORT ( ); END COMPONENT ;,COMPONENT nand2 PORT(a,b :IN STD_
10、LOGIC; y :OUT STD_LOGIC); END COMPONENT;,17,Configuration,決定使用那一個Architecture 語法:,CONFIGURATION c_name OF e_name IS - configurations END c_name ;,18,Example : R-S Latch,ENTITY rsff IS PORT(set,reset:IN BIT; q,qb:BUFFER BIT); END rsff; ARCHITECTURE netlist OF rsff IS COMPONENT nand2 PORT(a,b:IN BIT;
11、c:OUT BIT); END COMPONENT; BEGIN U1:nand2 PORT MAP(set,qb,q); U2:nand2 PORT MAP(reset,q,qb); END netlist;,Symbol,Schematic,19,Port Mapping,Mapping with order (pre-example) Mapping with name association Example:,U1: nand2 PORT MAP(a=set ,b=qb, c=q); U2: nand2 PORT MAP(c=qb, a=reset, b=q);,20,VHDL Ope
12、rator,Comparison Operator Logic Declaration Arithmetic Operator Bitwise Operator,21,Logic Declaration,AND OR NOT NOR NAND XOR XNOR 邏輯運算子可以應用在三種資料型態：BIT, BOOLEAN 和STD_LOGIC,22,Logic Operators,library ieee; use ieee.std_logic_1164.all; ENTITY log_ex IS PORT( A,B :in std_logic_vector(0 to 3); Y :out st
13、d_logic_vector(0 to 3); Z :out std_logic); end log_ex;,architecture a of log_ex is begin Y(0) = A(0) AND B(0) ; Y(1) = A(1) OR B(1) ; Y(2) = A(2) NOR B(2) ; Y(3) = A(3) XOR B(3) ; Z = (not A(0) nand B(0); end A;,Logic operators(應用在三種資料型態：BIT, BOOLEAN 和STD_LOGIC): not and or xor nand xnor,23,Relation
14、al operators,Relational operators: = , /= , , = Operands must be of the same type,library ieee; use ieee.std_logic_1164.all; ENTITY rel_ex IS PORT( A,B,C,D,E,F:in std_logic_vector(2 downto 0); Y: out std_logic); end rel_ex;,architecture behavior of rel_ex is begin process(A,B,C,D,E,F) begin if(A=B)
15、or (CD) and not(E=F) then y=1; else y=0; end if; end process; end behavior;,24,Arithmetic Operator,所有Synthetizer都支援 “+” : 加法 “-” : 減法 有些Synthetizer支援 “ * ” : 乘法 “ABS” : 求絕對值 編譯時設定數值運算時使用 “/” : 除法 “*” : 次方 “MOD” : 求模數 “REM” : 求餘數,25,Bitwise Operator,SLA,SRA,SLL,SRL,ROL,ROR,A sll 2 為 “01010100” A srl
16、3 為 “00010010” A sla 3 為 “10101111” A sra 2 為 “11100101” A rol 3 為 “10101100” A ror 5 為 “10101100”,26,Arithmetic Operators,Arith. operators: + (加) - (減) * (乘) / (除) *(次方),library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Std_logic_unsigned.all; entity arith_ex is port(A,B : in integer range 7 downto 0; C,D : out integer range 64 downto 0; E,F,G : out integer range 7 downto 0); end arith_
