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1、数字集成电路,第九讲 互连问题,互连参数的影响, 降低可靠性, 影响性能 增加延时 增加功耗,参数的分类, 电容, 电阻, 电感,9.2 INTERCONNECT,Dealing with Capacitance,9.2.1电容串扰效应,电容串扰效应 动态节点,3 x 1 mm overlap: 0.19 V disturbance,C,Y,C,XY,V,DD,PDN,CLK,CLK,In,1,In,2,In,3,Y,X,2.5 V,0 V,电容串扰效应 被驱动节点,tXY = RY(CXY+CY),Keep time-constant smaller than rise time,V (Vo
2、lt),0,0.5,0.45,0.4,0.35,0.3,0.25,0.2,0.15,0.1,0.05,0,1,0.8,0.6,t (nsec),0.4,0.2,X,Y,V,X,R,Y,C,XY,C,Y,tr,克服电容串扰的方法,避免浮空节点 对串扰敏感的节点，如预充电总线等，应当增加保持器件以降低阻抗 敏感节点应当很好地与全摆幅信号隔离 在满足时序约束的范围内尽可能加大上升（下降）时间 这会对短路功耗有影响 在敏感的低摆幅布线网络中采用差分信号传输方法，使串扰信号变为不会影响电路工作的共模干扰信号 同一层上的两条导线平行走线的距离不要太长，减小线间电容 两个信号之间增加屏蔽线，能有效地使线间电
3、容变为一个接地电容，从而消除干扰 不同层上信号之间的线间电容可以通过增加额外的布线层来进一步减小,屏蔽,GND,GND,屏蔽线,衬底 (,GND,),屏蔽层,V,DD,9.2.2串扰与性能,Cc,- 当相邻的信号线向相反的方向翻转时，延时增加 延时依赖于相邻信号线的活动,Miller 效应 - Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV
4、),串扰对延时的影响,r is ratio between capacitance to GND and to neighbor,在最坏情况下，g5，表明仅仅由于线上翻转方向的影响，导线延时和最好情形之间就可以有500的差别！,tp,k=gCw(0.38Rw+0.69RD) Cw=cwL; Rw=rwL,解决方法（I）,估计和改进：经过细致的参数提取和模拟可以确定延时的瓶颈，然后对电路进行适当的修改 最常使用的方法。 缺点：在整个设计生产过程中需要多次的反复，费时 能动性的版图生成：在导线的布线程序中考虑相邻导线的影响，以保证满足性能方面的要求 很有吸引力 但是所要求的EDA工具非常复杂,解决
5、方法（2）,可预测的结构：使用预先定义的、已知的或保守的布线结构，保证电路既能满足设计者提出的技术要求，又能使串扰不会引起失效 密集型布线结构 避免最坏情形的产生 编解码技术,结构化可预测的连线结构,Example: Dense Wire Fabric (Sunil Kathri) Trade-off: 线间串扰电容小了40倍， 代价： 2% 的延时开销，5的面积和总电容开销 Also: FPGAs, VPGAs,数据编码消除最恶劣情形,Encoder,Decoder,Bus,In,Out,电容负载和电路性能,复杂的设计中单个门常常需要驱动很大的扇出，因而具有很大的电容负载 总线、时钟网络、全
6、局控制信号（set/reset) 存储器中的读写信号 最坏情形发生在芯片内外接口，此时负载有封装导线、印刷电路板导线、连接的器件的输入电容组成 片外负载可以大至50pF，是标准片上负载的数千倍,驱动大电容负载,Transistor Sizing Cascaded Buffers,使用级联缓冲器,CL = 20 pF,In,Out,1,2,N,0.25 mm process Cin = 2.5 fF tp0 = 30 ps,F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.97 ns,(See Chapter 5),输出缓冲器设计,Transistor Size
7、s for optimally-sized cascaded buffer tp = 0.97 ns,0.25 mm process, CL = 20 pF,需要一些栅极宽度大约为1.5mm的超大晶体管！ 无法接受，因为一个复杂芯片需要很多这样的驱动器！,解决方法,在大多数情况下并不需要达到最优的缓冲器延时。片外通信常常能以片上时钟速度的几分之一进行。 放宽延时要求仍然可以使片外时钟速度超过100MHz，但却大大降低了对缓冲的要求。,Delay as a Function of F and N,10,1,3,5,7,Number of buffer stages N,9,11,10,000,1
8、000,100,t,p,/,t,p,0,F,=,100,F,=,1000,F,=,10,000,tp/tp0,输出驱动设计,Trade off Performance for Area and Energy Given tpmax find N and f Area Energy,选择较大的f有助于减小面积,输出驱动器设计再次考虑,Transistor Sizes of redesigned cascaded buffer tp = 1.89 ns,大尺寸晶体管的实现,G(ate),S(ource),D(rain),Multiple,Contacts,small transistors in
9、parallel,Reduces diffusion capacitance Reduces gate resistance,大尺寸晶体管意味着很长的栅极连线，而较长的多晶硅线具有较高的电阻，从而降低了开关性能,Bonding Pad Design,Bonding Pad,Out,In,VDD,GND,100 mm,GND,Out,ESD Protection,When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potenti
10、als requires (large) charge flow through the pads Diodes sink this charge into the substrate need guard rings to pick it up.,ESD Protection,芯片封装,Bond wires (25m) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (100m in 0.25m technolo
11、gy), with large pitch (100m) Many chips areas are pad limited,Pad Frame,Layout,Die Photo,驱动器电路,An alternative is flip-chip: Pads are distributed around the chip The soldering balls are placed on pads The chip is flipped onto the package Can have many more pads,三态缓冲,互连,Dealing with Resistance,9.3电阻效应
12、的影响,We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gates,9.3.1 RI Introduced Noise,电源/地分布,使用第三层金属走电源/
13、地 (EV4),在EV4设计中，增加了又厚又宽的第三层金属线 Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing,Metal 3,Metal 2,Metal 1,Courtesy Compaq,4层金属方法 (EV5) 3,4层用于电源/地的走线,4th “coarse and thick” metal layer added to the t
14、echnology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal 90% of 3rd and 4th metals used for power/clock routing,Metal 3,Metal 2,Metal 1,Metal 4,Courtesy Compaq,2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance,6 层金属方法 EV6,Metal 4,Metal 2,Metal 1,RP2/Vdd,RP1/Vss,Metal 3,Courtesy Compaq
