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1、 APPLICATION NOTE REJ05B0365-0100Z/Rev.1.00 December 2003 Page 1 of 28 R8C/10 Group A Software control of I2C-BUS using General-purpose Ports 1. Abstract This application note describes a software control program of I2C-BUS and its application example. This program can be also used for a control of
2、EEPROM. 2. Introduction A single master I2C-BUS can be controlled by software using general-purpose ports. The external pull-up resistances should be attached toP12(SDA) and P13(SCL). Table 1 shows the functional performance of I2C-BUS interface. Table 1 Functional performance of single master I2C-B
3、US interface Item Functional Performance Communication mode Master transmission (single master) SCL Clock Frequency 100kHz approx. Note 1 This is a value for a CPU clock operated at 16MHz when no interrupt is used. When a CPU clock operates at other than 16MHz, some adjustment is necessary to set th
4、is value. This program can also be used when operating other microcomputers within the M16C family, provided they have the same SFR (Special Function Registers) as the R8C/10 microcomputers. However, some functions may have been modified. Refer to the Users Manual for details. Use functions covered
5、in this Application Note only after careful evaluation. R8C/10 Group A Software Control of I2C-BUS using General-purpose Ports REJ05B0365-0100Z/Rev.1.00 December 2003 Page 2 of 28 3. I2C-BUS 3.1 START Condition / STOP Condition (1) START Condition Change SDA from high to low when SCL is high. Later,
6、 change SCL to low. (2) STOP Condition Change SDA from low to high when SCL is high. Later, change SCL to low. Figure 1 shows a configuration of START condition generation timing, and Figure 2 shows a configuration of STOP condition generation timing. A list of START condition / STOP condition gener
7、ation timing is shown in Table 2 below. Table2 a list of START condition / STOP condition generation timing Timing START condition STOP condition Set up time 2.0s approx. 1.6s approx. Hold time 3.0s approx. 3.0s approx. Note 1 This is a value for a CPU clock operated at 16MHz when interrupt is not u
8、sed When a CPU clock operates at other than 16MHz, some adjustment is necessary to set this value. Figure 1 START condition generation timing SCL SDA Set up time Hold time Figure 2 STOP condition generation timing SCL SDA Set up time Hold time R8C/10 Group A Software Control of I2C-BUS using General
9、-purpose Ports REJ05B0365-0100Z/Rev.1.00 December 2003 Page 3 of 28 3.2 Data Input / Output (1) Data output Data is output to SDA pin. After data setup time passes, a clock is output from SCL pin. (”L”H”L”) (2) Data input Input data after driving SCL high, and then drive SCL low. Figure 3 shows a co
10、nfiguration of data input/output timing , and Table 3 shows a list of data input/output timing. Table 3 A list of data input / output timing Timing Data output Data input Setup time 3.3s approx. - Access time - Over 1s approx. Clock ”H” time 3.0s approx. 4.7s approx. Note 1 This is a value for a CPU
11、 clock operated at 16MHz when interrupt is not used When a CPU clock operates at other than 16MHz, some adjustment is necessary to set this value. Figure 3 A configuration of data input /output timing Setup time Access time SCL SDA Data output Data input Output Input Clock ”H” time Clock ”H” time R8
12、C/10 Group A Software Control of I2C-BUS using General-purpose Ports REJ05B0365-0100Z/Rev.1.00 December 2003 Page 4 of 28 3.3 Byte Format 1 byte consists of 8-bit-length data and 1-bit-length Acknowledge. Acknowledge is a signal to indicate whether data is normally transferred or not. When Acknowled
13、ge indicates “L”, data is normally transferred. When it is “H”, data is not normally transferred. When the master device transfers the data to the slave device, the master device releases SDA line (high- impedance) at the 9th transmit clock pulse and the slave device returns an acknowledge signal. W
14、hen the master device receives the data from the slave device, the slave device releases SDA line (high-impedance) at the 9th transmit clock pulse and the master device returns an acknowledge signal. Figure 4 shows a configuration of byte format. Figure 4 Byte Format Acknowledge D7 SCL SDA D6 D5 D4
15、D3 D2 D1 D0 ACK Data 1 2 3 45678 9 R8C/10 Group A Software Control of I2C-BUS using General-purpose Ports REJ05B0365-0100Z/Rev.1.00 December 2003 Page 5 of 28 4. Application Example(a control of EEPROM) Write / read the data to 2k-bit EEPROM(HN58X2402SI). In 7 bit addressing mode, Device Address Cod
16、e (A2,A1,A0)can be assigned by the lower 3 bit of Device Address Word. Figure 5 shows an example of connection between a microcomputer and EEPROM(HN58X2402SI). 4.1 Byte Write Write “Write Data” to an address (n) assigned to Memory Address(W7 to W0). Confirm Acknowledge and generate Stop Condition after 8-bit Write Data is output. R8C/10 Group P12 P13 SDA SCL A2 A1 A0 WP “L” HN58X2402SI Figure 5 An example of connection Figure 6 Byte Write S S: Start Condition P: Stop Conditi
