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1、锁相技术译文翻译英文原名：High Speed Digital Hybrid PLL Frequency Synthesizer译文：高速数字混合锁相环频率合成器年纪专业：08级通信工程 班姓名： 学号： 2011年 5月2日英文中文High Speed Digital Hybrid PLL Frequency SynthesizerAbstract：The conventional PLL(Phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-lo
2、op structure.The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this problem.It operates in high speed, but the hardware complexity and power consumption are other serious problems since the DLT (digital look-up t
3、able) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator).This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT.Also, a timing synchronization circuit makes the negligible
4、 overshoot and much shorter settling time for the ultra fast switching speed.Also, the hardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL.Key Words: PLL, DLT, Frequency synthesisI. INTRODUCTIONHigh speed frequency synthesis is very important a
5、nd is widely used in the electronic and communication system applications.In 1999, El-Ela proposed that additional signal which is a synchronized saw-tooth waveform from the D/A converter is injected into the VCO input of the conventional PLL frequency synthesizer for the high speed operation 1.Howe
6、ver, it needs the optimal slope and duration at every frequency synthesis.To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design.In 2001, H. G. Ryu proposed a simplified structure of the DDFS (direct digital frequency synthesizer)-driven PLL for the h
7、igh switching speed 2.However, there is a problem that the speed of the whole system is limited by PLL.Y. Fouzar proposed a PLL frequency synthesizer of dual loop configuration using frequency-to-voltage converter (FVC) 3.It has a fast switching speed by the PD (phase detector), FVC using output sig
8、nal of VCO and the proposed coarse tuning controller.However, H/W complexity is increased for the high switching speed.Also, it shows the fast switching characteristic only when the FVC works well.Another method is pre-tuning one which is called DH-PLL in this study 4.It has very high speed switchin
9、g property, but H/W complexity and power consumption are increased due to digital look-up table (DLT) which is usually implemented by the ROM including the transfer characteristic of VCO(voltage controlled oscillator).For this reason, this paper proposes a timing synchronization circuit for the rapi
10、d frequency synthesis and a very simple DLT replacement digital logic block instead of the complex ROM type DLT for high speed switching and low power consumption.Also, the requisite condition is solved in the proposed method. The fast switching operation at every the frequency synthesis process is
11、verified by the computer circuit simulation.II. DH-PLL synthesizerAs shown in Fig.1, the open-loop synthesizer is a direct frequency synthesis type that VCO generates the desired output by the FCW (frequency control word) input from the D/A converter.The digital frequency word which is produced from
12、 the ROM type DLT (digital look-up table) containing the VCO transfer characteristic goes into D/A converter that generates the DC value corresponding to the desired VCO frequency. Fig. 1. Open-loop frequency synthesizer.The DC value is already found by the voltage-frequency characteristics of VCO.T
13、his open-loop frequency synthesizer has fast switching speed.However, it has the big problems of stability and sensitivity due to the inherent properties of the open loop structure.Therefore, this synthesizer type is not so attractive that this synthesizer is not widely used.Fig. 2. Closed-loop PLL
14、frequency synthesizer.In Fig. 2, FCW (frequency control word) is the division ratio command for frequency synthesis.This structure is very popular and excellent in the aspects of the stability, variety and flexibility.Also, the spurious noise is smaller than other frequency synthesizer. It takes the
15、 longer acquisition time to jump into a new frequency so that the switching speed is low.The switching time gets longer as the generation frequency spacing is increased.DH-PLL frequency synthesizer is shown in Fig.3.Fig.3.DH-PLL using DLT (digital look-up table).The open-loop structure of the DLT and DAC is combined into the conventional PLL closed-loop structure.In the conventional PLL, the output voltage of LF is fed to the VCO.On the contrary, sum of DAC output voltage and the LF output voltage drives the VCO whenever FCW is changed.Therefore, unlike conventional PLL
