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1、1,P32 1-4,Draw a logic diagram for a full-adder .Name each logic gate.Draw a four-bit adder as a type.Draw the component is repeated,you can draw its sub-components once and refer to them elsewhere in the diagram.,2,P32 1-4 题目要求,(1)画出1位全加器的逻辑图 (2)给每一个逻辑门命名 (3) 由四个一位加器组成一个四位全加器 (4) 给四位全加器中的每一个器件命名 (5
2、) 画出器件层次化图（从四位全加器到逻辑门， 如有重复可在图上标注参考其它器件）,3,1位全加器真值表,4,逻辑表达式,5,1bit full adder schematic,6,4bit full adder schematic,A3 B3,A2 B2,A1 B1,A0 B0,cin,cout,Sum0,Sum1,Sum2,Sum3,a0,a1,a2,a3,7,A component hierarchy,4bit adder,a0,a1,a2,a3,n1,n2,x2,x1,n3,n4,identical to a0s subcells,8,p98 2-1,Draw the cross-sec
3、tion of the inverter shown below along a cut through the middle of the p-type and n-type transistors.,9,P98 2-1,P-tub,N-tub,n+,n+,p+,p+,poly,oxide,substrate,p-,n-,10,P98 2-2a,VdsVgsVt Linear region:IdKW/L(VgsVt)Vds0.5Vds2VdsVgsVt Saturation region: Id0.5KW/L(VgsVt) 2 From Table 2-4 Kn73A/V2 Vtn0.7V
4、VgsVt 3.30.72.6 (V) Vds=1V, 2V is linear region Vds=3.3V, 5V is saturation region,a)W/L5/2,Assuming that Vgs=3.3V,compute the drain current through n-type transistors of these sizes at Vds values of 1v,2V,3.3V,and 5V:,11,P98 2-2b-c,b)W/L8/2,c)W/L12/2,12,P98 2-2d,d)W/L25/2,13,P99 2-5,Justify(证明是正当的)
5、each of these design rules: 2 poly-poly spacing Prevents shorting of two poly wires b) No required poly-metal spacing Metal and poly are on different layers, so they will not touch if their geometries overlap c) 1 of diffusion and metal surrounding cut; Must make sure that metal fully covers the cut
6、 to ensure a lowresistance connection. Must also make sure that the via contacts only diffusion, not any of the tub surrounding the diffusion. d) 2 overhang of poly at transistor gate. Must make sure that the poly completely disconnects the source and drain regions, otherwise the transistor will be
7、shorted by a diffusion trace.,14,P99 2-6,Explain Why is ndiff-to-pdiff spacing so large? Ndiff and pdiff are in the different tub.The tub boundary represents a large change in doping, which cant be performed in a small area. b) Why is metal-metal spacing larger than poly-poly spacing? Because metal
8、is placed on after poly, there is more variation in the surface that the metal is placed on, therefore more possibility of shorting, thus the greater metal-metal spacing requirement. c) Why is metal2-metal2 spacing larger than metal1-metal1 spacing? Because metal2 is placed on after metal1, there is
9、 more variation in the surface that the metal2 is placed on, therefore more possibility of shorting, thus the greater metal2-metal2 spacing requirement.,15,P99 2-7,What distinguishes a tub tie from an ndiff-metal1 via?A tub tie connects to the tub and includes an extra diffusion of the same type as
10、the tub. For example,the tub tie next to the ndiff-metal1 via would use a p+ diffusion to connect to the tub.,16,P99 2-9,Compute the resistance and capacitance for each polysilicon wire below: a)Assume 1=0.25m Area=3.75m0.5m=1.875m2 Perimeter=3.75m2+0.5m2=8.5m P80 Table 2-4: C=0.09fF/m21.875m2+0.04
11、fF/m8.5m=0.51 fF R=4/7.5=30,15,2,17,P99 2-9,Compute the resistance and capacitance for each polysilicon wire below: b)Assume 1=0.25m Area=3.75m0.5m2+1m0.5m =4.25m2 Perimeter=3.75m2+3.25m2+0.5m2+1m+2m=18m C=0.09fF/m24.25m2+0.04 fF/m18m =1.1 fF R=4/6.52+4/2+4/1=64,15,2,2,4,18,P99 2-10,Compute the para
12、sitic resistance and capacitance of the source/drain region of transistors of the types and sizes given below,assuming that these source drain-regions have the required 3 overhang past the gate: a)p-type;W/L=3/2;b)n-type;W/L=4/2;c)p-type;W/L=6/2;d)n-type;W/L=12/2;,19,P99 2-10a,Use P80 table 2-4 Typi
13、cal parameters for 0.5um process: =0.25 , 3=0.75, a)p-type;W/L=3/2=0.75/0.5 perimeter: (0.75+0.75)2=3um area:0.75 0.75=0.5625um2 Cpdiff,bot = 0.9fF/ m2 Cpdiff,side =0.3fF/ m Rpdiff = 2 / Ctotal= 0.9 0.5625+ 0.3 3=1.4fF R= 2 ,20,P100 2-10b,Use P80 table 2-4 Typical parameters for 0.5um process: =0.25
14、 , 3=0.75, a)n-type;W/L=4/2=1/0.5 perimeter: (0.75+1)2=3.5um area:0.75 1=0.75um2 Cndiff,bot = 0.6fF/ m2 Cndiff,side =0.2fF/ m Rndiff = 2 / Ctotal= 0.6 0.75+ 0.2 3.5=1.2fF R= 2 0.75=1.5 ,21,P100 2-10c,Use P80 table 2-4 Typical parameters for 0.5um process: =0.25 , 3=0.75, a)p-type;W/L=6/2=1.5/0.5 per
15、imeter: (1.5+0.75)2=4.5um area:0.75 1.5=1.1um2 Cpdiff,bot = 0.9fF/ m2 Cpdiff,side =0.3fF/ m Rpdiff = 2 / Ctotal= 0.9 1.1+ 0.3 4.5=2.3fF R= 2 0. 5=1,22,P100 2-10d,Use P80 table 2-4 Typical parameters for 0.5um process: =0.25 , 3=0.75, a)n-type;W/L=12/2=3/0.5 perimeter: (0.75+3)2=7.5um area:0.75 3=2.2
16、5um2 Cndiff,bot = 0.6fF/ m2 Cndiff,side =0.2fF/ m Rndiff = 2 / Ctotal= 0.2 7.5+ 0.6 2.25=2.85fF R= 2 (0.753)=0.5 ,23,P101 2-13,Reverse-engineer the layout shown on next page.Draw: a stick diagram corresponding to the layout; a transistor schematic. Label inputs and outputs in your drawings in accordance(一致) with the labels in the layout.,
