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1、第 3 章 VHDL 基础 习题 3-1 如图所示 3-2 程序： IF_THEN 语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 S PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN PROCESS ( s0,s1,a,b,c,d ) BEGIN IF s1=0 AND s0=0 THEN y y
2、 y y y NULL ; END CASE ; END PROCESS ; END ARCHITECTURE two ; 3-3 程序： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MUXK IS PORT ( s0,s1 : IN STD_LOGIC ; a1,a2,a3 : IN STD_LOGIC ; outy : OUT STD_LOGIC ) ; END ENTITY MUXK ; ARCHITECTURE double OF MUXK IS SIGNAL tmp : STD_LOGIC ; -内部连接线 BEGIN p_
3、MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y ) SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ; BEGIN IF u1_s=0 THEN u1_y s_out s_out s_out s_out NULL ; END CASE ; END PROCESS ; END ARCHITECTURE fhd1 ; 或门逻辑描述： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY or IS PORT ( a,b : IN STD_LOGIC ; c : OUT S
4、TD_LOGIC ) ; END ENTITY or ; ARCHITECTURE one OF or IS BEGIN cx, y=y, diff=d, s_out=e ) ; u2 : h_suber PORT MAP ( x=d, y=sub_in, diff=diffr, s_out=f ) ; u3 : or PORT MAP ( a=f, b=e, c=sub_out ) ; END ARCHITECTURE fhd1 ; （2）8 位减法器： f_suber sub_in x ysub_out diffr 0 x 0 y 0 f_suber sub_in x ysub_out d
5、iffr 1 x 1 y 1 f_suber sub_in x ysub_out diffr 2 x2 y 2 f_suber sub_in x ysub_out diffr 3 x 3 y 3 f_suber sub_in x ysub_out diffr 4 x 4 y 4 f_suber sub_in x ysub_out diffr 5 x 5 y 5 f_suber sub_in x ysub_out diffr 6 x 6 y 6 f_suber sub_in x ysub_out diffr 7x 7 y 7sub_out a b c d e f g u0 u1 u2 u3 u4
6、 u5 u6 u7LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY 8f_suber IS PORT ( x0,x1,x2,x3,x4,x5,x6,x7 : IN STD_LOGIC ; y0,y1,y2,y3,y4,y5,y6,y7 : IN STD_LOGIC ; sub_in : IN STD_LOGIC ; sub_out : OUT STD_LOGIC ; diffr0,diffr1,diffr2,diffr3 : OUT STD_LOGIC ; diffr4,diffr5,diffr6,diffr7 : OUT STD_LOGI
7、C ) ; END ENTITY 8f_suber ; ARCHITECTURE 8fhd1 OF 8f_suber IS COMPONENT f_suber IS PORT ( x,y,sub_in : IN STD_LOGIC ; sub_out ,diffr : OUT STD_LOGIC ) ; END COMPONENT f_suber ; SIGNAL a,b,c,d,e,f,g : STD_LOGIC ; BEGIN u0 : f_suber PORT MAP ( x=x0, y=y0, sub_in=, sub_out=a, diff=diff0 ) ; u1 : f_sube
8、r PORT MAP ( x=x1, y=y1, sub_in=a, sub_out=b, diff=diff1 ) ; u2 : f_suber PORT MAP (x=x2, y=y2, sub_in=b, sub_out=c, diff=diff2 ) ; u3 : f_suber PORT MAP (x=x3, y=y3, sub_in=c, sub_out=d, diff=diff3 ) ; u4 : f_suber PORT MAP (x=x4, y=y4, sub_in=d, sub_out=e, diff=diff4 ) ; u5 : f_suber PORT MAP (x=x
9、5, y=y5, sub_in=e, sub_out=f, diff=diff5 ) ; u6 : f_suber PORT MAP (x=x6, y=y6, sub_in=f, sub_out=g, diff=diff6 ) ; u7 : f_suber PORT MAP (x=x7, y=y7, sub_in=g, sub_out= sub_out, diff=diff7 ) ; END ARCHITECTURE 8fhd1 ; 3-5 程序： 或非门逻辑描述： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nor IS PORT
10、( d,e : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END ENTITY nor ; ARCHITECTURE one OF nor IS BEGIN f c, e=CL, f=a ) ; u1 : DFF1 PORT MAP ( CLK=CLK0, D=a, Q=b ) ; u2 : not PORT MAP ( g=b, g=c, h=OUT1 ) ; END ARCHITECTURE one ; 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 程序 1： SIGNAL A,EN : STD_LOGIC ; PROCE
11、SS ( A, EN ) VARIABLE B : STD_LOGIC ; BEGIN IF EN = 1 THEN B := A ; END IF ; END PROCESS ; 程序 2： ARCHITECTURE one OF sample IS VARIABLE a,b,c : BEGIN c := a+b ; END ARCHITECTURE one ; 程序 3： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS PORT ( a,b : IN STD_LOGIC ; sel : IN STD_LOGIC ;
12、c : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN IF sel = 0 THEN c IF DATAIN = “10” THEN N_ST IF DATAIN = “11” THEN N_ST IF DATAIN = “01” THEN N_ST IF DATAIN = “00” THEN N_ST IF DATAIN = “11” THEN N_ST N_ST IF DATAIN = 1 THEN STX IF DATAIN = 0 THEN STX IF DATAIN = 1 THEN STX IF DATAIN = 0 THEN STX IF DATAIN = 1 THEN STX STX显式表达； STD ：STANDARD、TEXTIO 无须显式表达； WORK ：无须显式表达，总是可见； VITAL ：VITAL_TIMING、VITAL_PRIMITIVES 8-12 8-13 8-14 8-15
