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1、Chapter 1 Computer System Overview,Dave Bremer Otago Polytechnic, N.Z. 2008, Prentice Hall,Operating Systems: Internals and Design Principles, 6/E William Stallings,Roadmap路标,Basic Elements基本构成 Processor Registers处理器寄存器 Instruction Execution指令的执行 Interrupts中断 The Memory Hierarchy存储器的层次 Cache Memory高
2、速缓存 I/O Communication TechniquesI/O通讯技术,Operating System操作系统,Exploits the hardware resources of one or more processors利用硬件资源的一个或多个处理器 Provides a set of services to system users为用户提供一组服务 Manages secondary memory and I/O devices管理辅助存储器和I/O设备,A Computers Basic Elements电脑的基本构成,Processor处理器 Main Memory内存
3、 I/O Modules输入输出模块 System Bus系统总线,Processor处理器,Controls operation, performs data processing控制操作，执行数据处理 Two internal registers两个内部寄存器 Memory address resister (MAR)地址寄存器 Memory buffer register (MBR)缓冲寄存器 I/O address registerI/O地址寄存器 I/O buffer registerI/O缓冲寄存器,Main Memory内存,Volatile易失的 Data is typical
4、ly lost when power is removed Referred to as real memory or primary memory 被称作实存储器或主存储器 Consists of a set of locations defined by sequentially numbers addresses由一组单元组成，这些单元由顺序编号的地址定义 Containing either data or instructions存放数据或指令,I/O ModulesI/O模块,Moves data between the computer and the external envir
5、onment such as: Storage (e.g. hard drive)存储器（例如硬盘） Communications equipment通信设备 Terminals终端 Specified by an I/O Address Register由I/O地址寄存器确定 (I/OAR)（I/O地址寄存器）,System Bus,Communication among processors, main memory, and I/O modules在处理器内存和I/O模块间通讯,Top-Level View顶层视图（P7）,Roadmap,Basic Elements Processor
6、 Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Processor Registers,Faster and smaller than main memory比内存快、小 User-visible registers用户可见寄存器 Enable programmer to minimize main memory references by optimizing register use通过优先使用寄存器减少内存访问 Contro
7、l and status registers控制和状态寄存器 Used by processor to control operating of the processor用以控制处理器的操作 Used by privileged OS routines to control the execution of programs由特权操作系统例程使用以控制程序执行,User-Visible Registers用户可见寄存器,May be referenced by machine language可以通过机器语言引用 Available to all programs application p
8、rograms and system programs对所有程序可用（包括应用程序和系统程序） Types of registers typically available are:通常可用的寄存器类型有： data, address, condition code registers.条件码寄存器,Data and Address Registers数据和地址寄存器,Data Often general purpose常常通用 But some restrictions may apply有时会有限制 Address Index Register变址寄存器 Segment pointer堆指
9、针 Stack pointer栈指针,Control and Status Registers控制和状态寄存器,Program counter (PC)程序计数器 Contains the address of an instruction to be fetched包含将取指令的地址 Instruction register (IR)指令寄存器 Contains the instruction most recently fetched包含最近取用的指令 Program status word (PSW)程序状态字 Contains status information包含状态信息,Cond
10、ition codes条件码,Usually part of the control register通常控制寄存器的一部分 Also called flags也称为标记 Bits set by processor hardware as a result of operations处理器硬件为操作结果设置的位 Read only, intended for feedback regarding the results of instruction execution.只读，用于反馈指令执行结果,Roadmap,Basic Elements Processor Registers Instru
11、ction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Instruction Execution指令的执行,A program consists of a set of instructions stored in memory处理器执行的程序由一组存储在内存中的指令组成 Two steps两个步骤 Processor reads (fetches) instructions from memory处理器从内存中读取指令 Processor executes each
12、instruction处理器执行每一条指令,Basic Instruction Cycle基本指令周期,Instruction Fetch and Execute取指令和执行指令,The processor fetches the instruction from memory处理器从内存中读取指令 Program counter (PC) holds address of the instruction to be fetched next程序计数器保存下一条将取指令的地址 PC is incremented after each fetch每次取指令后程序计数器自增,Instruction
13、 Register指令寄存器,Fetched instruction is loaded into instruction register取到的指令载入到指令寄存器 Categories操作分类 Processor-memory, 处理器-存储器 processor-I/O, 处理器-I/O Data processing, 数据处理 Control控制,Characteristics of a Hypothetical Machine理想机器的特征,Example of Program Execution程序执行的例子,Roadmap,Basic Elements Processor Re
14、gisters Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques,Interrupts中断,Interrupt the normal sequencing of the processor中断处理器正常序列 Provided to improve processor utilization用于提高处理器效率 Most I/O devices are slower than the processor Processor must pause to wai
15、t for device,Common Classes of Interrupts中断的通常等级,Flow of Control without Interrupts无中断控制流程,Interrupts and the Instruction Cycle终端和指令周期,Transfer of Control via Interrupts通过中断的控制转移,Instruction Cycle with Interrupts有中断的指令周期,Short I/O Wait短I/O等待,Long I/O wait长I/O等待,Simple Interrupt Processing简单的中断处理,Cha
16、nges in Memory and Registers for an Interrupt内存和寄存器因中断而产生的变化,Multiple Interrupts多中断,Suppose an interrupt occurs while another interrupt is being processed.假设当一个中断正在处理，另一个中断出现 E.g. printing data being received via communications line. Two approaches:两个方法 Disable interrupts during interrupt processing
17、在一个中断处理中禁止其他中断 Use a priority scheme.使用优先级,Sequential Interrupt Processing顺序中断处理,Nested Interrupt Processing嵌套中断处理,Example of Nested Interrupts嵌套中断的例子,Multiprogramming多道程序设计,Processor has more than one program to execute处理器有多个程序要执行 The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O程序的执行顺序取决于他们的相对优先级以及是否正在等待I/O After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt一个中断处理完成后，控制权可能不会立刻返回到中断时执行到的程序（而可能转移到其他待运行的具有更高优先级的其他程序）,
