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1、通过设置 XS128 的锁相环，可以方便改变内部总线频率，轻松实现超频。下面是16MHz120MHz的设置函数，后面有各寄存器用法。void SetBusCLK_16M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR=0x00 | 0x01; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_32M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0x40
2、| 0x03; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_40M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x04; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_48M(void)
3、CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x05; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_64M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x07; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLK
4、SEL_PLLSEL =1; void SetBusCLK_80M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x09; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_88M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x0a; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop)
5、; _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_96M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x0b; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_104M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x0c; R
6、EFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; void SetBusCLK_120M(void) CLKSEL=0X00; PLLCTL_PLLON=1; SYNR =0xc0 | 0x0d; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1; S12XECRG Clock Select Register (C
7、LKSEL ) 先把第 7 位置 0，即 PLLSEL 0，System clocks are derived from OSCCLK(fbus=fosc/2) 即系统总线时钟由提供外部晶振提供，系统内部总线频率=OSCCLK/2 （OSCCLK为外部晶振频率）当 PLLSEL 1 时， System clocks are derived from PLLCLK(fBUS = fPLL / 2) 即系统总线时钟由锁相环提供，系统内部总线频率=PLLCLK/2 （PLLCLK 为锁相环倍频后的频率）。S12XECRG IPLL Control Register (PLLCTL ) PLLCTL_
8、PLLON=1时， IPLL is turned on，即打开 PLL 电路S12XECRG Synthesizer Register (SYNR ) S12XECRG Reference Divider Register (REFDV ) 根据想要的时钟频率设置SYNR 和 REFDV 两个寄存器，只有当CLKSEL_PLLSEL=0时才能写入S12XECRG Post Divider Register (POSTDIV ) If POSTDIV = $00 then fPLL is identical to fVCO (divide by one). 即此时 PLLCLK=2*OSCCLK
9、*(SYNR+1)/(REFDV+1) PLLCLK 为 PLL 模块输出的时钟频率； OSCCLK 为晶振频率；SYNR 、 REFDV 分别为寄存器SYNR 、 REFDV中的值。S12XECRG Flags Register (CRGFLG ) LOCK 为只读位0 VCOCLK is not within the desired tolerance of the target frequen 1 VCOCLK is within the desired tolerance of the target frequency.即当 PLL 稳定时置 LOCK 1 要想知道其他位的用法，请参考XS128 的 datasheet ，或留言。
