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1、Enabling success from the center of technologyCopyright 2006 Avnet Inc.Xilinx Improving Performance WorkshopFeaturing ISE 8.1 ToolsVer 0.1Objectives This course will teach digital designers how to analyze design performance and achieve timing closure through the use of timing reports What you will l
2、earn Timing closure methodology Constraint usage and entry Timing analysis tools Implementation tools and usage2Ver 0.1AgendaDesign / Tools Flow Overview Timing Closure Flow Fundamental Timing Constraints Lab1: Synthesis Options and Fundamental Constraints Advanced Timing Constraints Clock Considera
3、tions Tools Options and Switches Cross Probing Xplorer Tool Lab2: Problem Solving with Advanced Constraints and Tools Options3Ver 0.1ISE Tool Flow OverviewImplementation ConstraintsSiliconDesign EntrySynthesisDelay SimulationFloor-PlanningMap Place TIMEGRP ADDR_IN_GRP OFFSET = IN 15 AFTER clk50; NET
4、 ADDR_ TNM = ADDR_OUT_GRP; TIMEGRP ADDR_OUT_GRP OFFSET = OUT 35 BEFORE clk50;39Ver 0.1Exclusion of Elements Subgroups created based on names with “EXCEPT” keyword Example Assume design has several data busses that all start with “DATA” Use the EXCEPT command to create a group with all the pads excep
5、t the data pads TIMEGROUP CTRL_PADS = PADS EXCEPT (DATA*); TIMEGROUP DATAPINS = PADS(DATA*); TIMESPEC TS_IO1=FROM CTRL_PADS TO FFS 20; TIMESPEC TS_IO2=FROM FFS TO CTRL_PADS 20; TIMESPEC TS_IO3=FROM CTRL_PADS TO CTRL_PADS 30; TIMESPEC TS_IODATA=FROM DATAPINS TO FFS 15; EXCEPT can be used with Area Gr
6、oups, Time Groups, and Component Groups40Ver 0.1Ignoring Paths The TIG constraint removes any constraints from being applied to the specified path Paths can be specified between groups Shows up in timing report Nets can be specified Does not show up in timing report Example TIMESPEC TS_IGNORE = FROM
7、 GROUP1 TO GROUP2 TIG ; NET SLOW_NET TIG; Improves run times by removing unnecessary PAR effort41Ver 0.1Ignoring Paths (TIG) Syntax Syntax NET|PIN|INST name TIG = group1 group2 ;name is the element, net, or instance name that is to be ignored group_name is an option field which ignores the net, inst
8、ance, or pin in the listed group All paths that fan forward from the net or instance will not have any timing constraints applied to them The paths will be treated as if they dont exist ExamplesIgnore a signal of the design NET CHIP_MODE TIG; Ignore a signal from a specific timespec NET SLOW_SIG TIG
9、=TS_01; Ignore false paths between synchronous elements TIMESPEC TS_TIG1=FROM FFS(REGA*) TO FFS(REGB*) TIG; Note: May have to use TNM or TNM_NET to create groups. 42Ver 0.1Multi-Cycle Path Allows user to pull these paths out of global period constraints when multiples of the period is all that is re
10、quired Example NET CLK TNM_NET = CLK_GRP; TIMESPEC TS_CLK = PERIOD CLK_GRP 10 ns; INST RAM TNM = RAM_GRP; INST LATCH TNM = LATCH_GRP; TIMESPEC TS_SLOW = FROM RAM_GRP TO LATCH_GRP CLK_GRP * 2;D QCLKDFFRAMBUFGD QGLATCHD QDFF D QDFF43Ver 0.1Multi-cycle/FROM:TO Constraint The FROM:TO constraint covers p
11、aths between groups taking clock skew into account It is used to constrain the following types of paths Multi-cycle paths -If not expected to meeting the original single cycle clock period Data paths between unrelated clocks False Paths -If paths/net that are known not to have a timing requirement N
12、o HOLD violation check is done for FROM:TO paths= Constrained Data PathBUFGCLKAADATAOUT2OUT1QFLOP3DQFLOP1DQFLOP5DQFLOP4DBUS 70CDATAQFLOP2DBUFGCLKB= Unconstrained Data Path44Ver 0.1FROM THRU TO Allows user to select unique path between synchronous elements when numerous paths exist Constrains the pat
13、h through specific logic The TPTHRU attribute is attached to net/instance/macro NET $3M17/ON_THE_WAY TPTHRU = ABC; TIMESPEC TS_FIFOS=FROM RAMS(FIFORAM) THRU ABC TO FFS(MY_REG*) 25;FIFORAMMYFIFOQDQDQDMY_REG_0MY_REG_1MY_REG_2reg0reg1reg2TPTHRU=abc45Ver 0.1Area Groups Area groups are used to specify a
14、group of logical blocks that are packed into separate physical areas by the mapper- INST AREA_GROUP = ; For Virtex-E/II/IIP/Spartan-II architecture, both TBUFs and SLICES are supported If the AREA_GROUP is attached to a hierarchical block, all logical blocks within that block are assigned to the gro
15、up If a symbol contains a LOC and is part of an area group, the LOC constraint will take priority and the symbol will be removed from the area group Timegrps can be used to create area groups, more detail to follow46Ver 0.1Area Groups After defining the area group, the range of the group, and compre
16、ssion of the group into a percentage of the total CLBs can be defined- AREA_GROUP RANGE = ;- AREA_GROUP COMPRESSION = ;- The defines the physical area for the area group.- If the logic in the group exceeds the range, map will error.- The defines the percentage of CLBs within the particular to compress the logic of the area group into Area groups with a
