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1、嵌入式處理器架構與程式設計王建民 中央研究院 資訊所 2008年 7月ContentsnIntroductionnComputer ArchitecturenARM ArchitecturenDevelopment Tools:GNU Development ToolsnARM Instruction SetnARM Assembly LanguagenARM Assembly Programming:GNU ARM ToolChainnInterrupts and Monitor2Lecture 10 Interrupts and MonitorOutlinenException Handl
2、ing and Software InterruptsnELF: Executable and Linking FormatnARM Monitor and Program Loading4Normal Program Flow vs. ExceptionnNormally, programs execute sequentially (with a few branches to make life interesting) nNormally, programs execute in user mode nExceptions and interrupts break the sequen
3、tial flow of a program, jumping to architecturallydefined memory locations nIn ARM, SoftWare Interrupt (SWI) is the “system call” exception5ARM ExceptionsnTypes of ARM exceptions lReset: when CPU reset pin is asserted lundefined instruction: when CPU tries to execute an undefined opcode lsoftware in
4、terrupt: when CPU executes the SWI instruction lprefetch abort: when CPU tries to execute an instruction prefetched from an illegal addressldata abort: when data transfer instruction tries to read or write at an illegal address lIRQ: when CPUs external interrupt request pin is asserted lFIQ: when CP
5、Us external fast interrupt request pin is asserted 6The Programmers ModelnProcessor Modes (of interest)lUser: the “normal” program execution mode.lIRQ: used for generalpurpose interrupt handling.lSupervisor: a protected mode for the operating system.nThe Register SetlRegisters R0R15 + CPSRlR13: Stac
6、k Pointer (by convention)lR14: Link Register (hardwired)lR15: Program Counter where bits 0:1 are ignored (hardwired)7TerminologynThe terms exception and interrupt are often confused nException usually refers to an internal CPU eventlfloating point overflow lMMU fault (e.g., page fault) ltrap (SWI) n
7、Interrupt usually refers to an external I/O eventlI/O device request lreset nIn the ARM architecture manuals, the two terms are mixed together8What do SWIs do?nSWIs (often called software traps) allow a user program to “call” the OS that is, SWIs are how system calls are implemented. nWhen SWIs exec
8、ute, the processor changes modes (from User to Supervisor mode on the ARM) and disables interrupts. 9SWI ExamplenTypes of SWIs in ARM Angel (axd or armsd)lSWI_WriteC(SWI 0) Write a byte to the debug channel lSWI_Write0(SWI 2) Write the nullterminated string to debug channel lSWI_ReadC(SWI 4) Read a
9、byte from the debug channel lSWI_Exit(SWI 0x11) Halt emulation this is how a program exits lSWI_EnterOS(SWI 0x16) Put the processor in supervisor mode lSWI_Clock(SWI 0x61) Return the number of centiseconds lSWI_Time(SWI 0x63) Return the number of secs since Jan. 1, 197010What happens on an SWI?1nThe
10、 ARM architecture defines a Vector Table indexed by exception type nOne SWI, CPU does the following: PC :8000:e1a0c00d movip, sp8004:e92ddff8 stmdbsp!, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr, pc8008:e24cb004 subfp, ip, #4; 0x4800c:eb000023 bl80a0 8010:eb000c2d blb0cc 8014:e24bd028 subsp, fp, #40
11、; 0x288018:e89d6ff0 ldmiasp, r4, r5, r6, r7, r8, r9, sl, fp, sp, lr801c:e1a0f00e movpc, lr Disassembly of section .text:00008020 :8020:e92d4030 stmdbsp!, r4, r5, lr8024:e59f505c ldrr5, pc, #92; 8088 8028:e5d53000 ldrbr3, r5802c:e3530000 cmpr3, #0; 0x08030:18bd8030 ldmneiasp!, r4, r5, pc8034:e59f4050
12、 ldrr4, pc, #80; 808c 8038:e5943000 ldrr3, r4803c:e5932000 ldrr2, r38040:e3520000 cmpr2, #0; 0x08044:0a000007 beq8068 8048:e2833004 addr3, r3, #4; 0x4Initialization code62Listing from armelfobjdump2804c:e5843000 strr3, r48050:e1a0e00f movlr, pc8054:e12fff12 bxr28058:e5943000 ldrr3, r4805c:e5932000 l
13、drr2, r38060:e3520000 cmpr2, #0; 0x08064:1afffff7 bne8048 8068:e59f3020 ldrr3, pc, #32; 8090 806c:e3530000 cmpr3, #0; 0x08070:159f001c ldrner0, pc, #28; 8094 8074:11a0e00f movnelr, pc8078:112fff13 bxner3807c:e3a03001 movr3, #1; 0x18080:e5c53000 strbr3, r58084:e8bd8030 ldmiasp!, r4, r5, pc8088:0000bb
14、88 andeqfp, r0, r8, lsl #23808c:0000b248 andeqfp, r0, r8, asr #48090:00000000 andeqr0, r0, r08094:0000bb70 andeqfp, r0, r0, ror fp00008098 :8098:e52de004 strlr, sp, #4!809c:e49df004 ldrpc, sp, #4000080a0 :63Listing from armelfobjdump380a0:e59f303c ldrr3, pc, #60; 80e4 80a4:e3530000 cmpr3, #0; 0x080a
15、8:e52de004 strlr, sp, #4!80ac:e59f0034 ldrr0, pc, #52; 80e8 80b0:e59f1034 ldrr1, pc, #52; 80ec 80b4:11a0e00f movnelr, pc80b8:112fff13 bxner380bc:e59f002c ldrr0, pc, #44; 80f0 80c0:e5903000 ldrr3, r080c4:e3530000 cmpr3, #0; 0x080c8:e59f3024 ldrr3, pc, #36; 80f4 80cc:049df004 ldreqpc, sp, #480d0:e3530
16、000 cmpr3, #0; 0x080d4:049df004 ldreqpc, sp, #480d8:e1a0e00f movlr, pc80dc:e12fff13 bxr380e0:e49df004 ldrpc, sp, #480e4:00000000 andeqr0, r0, r080e8:0000bb70 andeqfp, r0, r0, ror fp80ec:0000bb8c andeqfp, r0, ip, lsl #2380f0:0000bb84 andeqfp, r0, r4, lsl #2380f4:00000000 andeqr0, r0, r0000080f8 :80f8:e52de004 strlr, sp, #4!64Listing from armelfobjdump480fc:e49df004 ldrpc, sp, #400008100 :8100:e3a00016 movr0, #22;
