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1、Bistable Elements（双稳态元件）QQ_LIt has two stable states：Q = 1 and Q = 0 bistable circuit（双稳电路）When power is first applied to the circuit, it randomly comes up in one state or the other and stays there forever.1亚稳态的存在使电路的状态可能出现不确定性。稳态稳态亚稳态 Random noise will tend to drive a circuit that is operating at t
2、he metastable point toward one of the stable operating points. 从一个“稳态”转换到另一个“稳态”需加一定宽度的脉冲（足够的驱动）。Metastable Behavior（亚稳态特性）Vin1Vout1= Vin2= Vout22S-R LatchS QR QNLogic symbolResetSet清0置10 0 0 1 1 0 1 1S Rlast state 0 1 1 0 0 0Q QNFunction tableS QR QQQNRS0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1
3、 1S R0 1 0 0 1 1 0 0QQ*状态转移真值表3S - R LatchS_L = R_L = 11 1 1 0 0 1 0 0S_L R_Llast state 0 1 1 0 1 1Q QNFunction tableretain previous stateS_L = 1, R_L = 0Q = 0, QN = 1S_L = 0, R_L = 1Q = 1, QN = 0S_L = R_L = 0Q=QN=1，不定状态SR清 0置 1 禁止状态S QR QLogic symbolQQNS_LR_L4S-R Latch with EnableSRC0 X X 1 0 0 1 0
4、 1 1 1 0 1 1 1C S Rlast state last state 0 1 1 0 1 1Q QNFunction table(1) C = 0,retain previous state(2) C = 1,like an S-R latch注意：当S=R=1时，若C由10，则下一状态不可预测。QQNS_LR_L清 0置 1禁止状态S C RQQLogic symbol5D LatchD = 1时，Q = 1C = 0，QQNSRDC输出状态保持不变； 输出随输入状态而改变。C = 1，D = 0时，Q = 0Q = D transparent latch 透明锁存器D QC Q
5、Logic symbolC D Q QN1 0 0 1 1 1 1 00 XFunction tablelast state6QDCtpLH(CQ)tpHL(DQ)tpLH(DQ) tpHL(CQ)tsetupsetup time 建立时间tholdhold time 保持时间 There is a window of time around the falling edge of C when the D input must not change. propagation delay: tpLH(CQ) , tpHL(CQ) , tpHL(DQ) , tpLH(DQ)D Latch Typ
6、ical operation7Application of LatchD Q C QD Q C QD Q C QD Q C QDIN3:0 WRDOUT3:0RDmemory unit8只用一片1位全加器实现？X Y CI CO SX Y CI CO SX Y CI CO SC0S0S1SnX0 Y0X1 Y1Xn Yn串 行 加 法 器C1C2C1S0X0 Y0C0X Y CI CO SC2S1X1 Y1C1反馈C3S2X2 Y2C2利用反馈和时钟控制Application of LatchIterative Circuit9X Y CI CO SX Y CI CO SX Y CI CO S
7、C0S0S1SnX0 Y0X1 Y1Xn Yn串 行 加 法 器C1C2暂存X Y CI CO SCi+1SiXi YiCi时钟控制利用锁存器暂存运算结果。Application of LatchIterative Circuit10暂存X Y CI CO SCi+1SiXi YiCi时钟控制利用锁存器暂存运算结果。Q D Q CX Y CISi Ci+1Xi Yi CiS COCLK串行输入、串行输出需要有效的时钟控制Application of LatchIterative Circuit11D Flip-flop （D触发器）D Q C QD Q C QQQNDCLK(1) CLK=0时
8、，(2) CLK=1时，主锁存器工作，接收输入信号 Qm=D;从锁存器不工作，输出 Q 保持不变.主锁存器不工作，Qm 保持不变;从锁存器工作，将 Qm 传送到输出端.主 master从 slave Qm12DCLKQQmD Q C QD Q C QQQNDCLK主 master从 slave QmD Flip-flop （D触发器）13DCLKQD CLK Q QN0 0 1 1 1 0 X 0 last state X 1 last statefunction tableD QCLK Qlogic symboledge-triggered behaviorPositive-edge-tri
9、ggered D flip-flop (正边沿触发式D触发器)sample the D input only at the rising edge of a CLK signal.characteristic equation （特征方程） Q*=D“*”表示时钟触发沿到 来后输出Q的新状态。14DCLKQDC QD触发器 边沿有效D锁存器 电平有效15CLKQtpLH(CQ)tpHL(CQ) tsetupSetup timethold Hold timel Timing Behavior propagation delay (CLKQ) It has a setup and hold tim
10、e window during which the D inputs must not change.16D Q C QD Q C QQ QNDCLKD QCLK QD CLK Q QN0 0 1 1 1 0 X 0 last state X 1 last statefunction table logic symbol Negative-edge-triggered D flip-flop （负边沿触发式D触发器）17CLKQQLDPR_LCLR_LPR D QCLK Q CLRPR (preset), CLR (clear)asynchronous inputs（异步输入端）通常用于初始化
11、电路状态、测试等。 D flip-flop with preset and clear （具有预置和清零端的D触发器）18 EN=1 (asserted),select the external D input; EN=0 (negated),select the current output.D Q EN CLK Qlogic symbolD QCLK QD ENCLKQ QL2-to-1 MUX (2选1电路)Q*=DI=END+ ENQ （状态在时钟触发沿后改变）DI Edge-Triggered D Flip-Flop with Enable （具有使能端的D触发器）Character
12、istic Equation（特征方程）function table Fig. 7-2119D QCLK QD TECLKQ QLTI TE = 0 normal modeselect the external D input; TE = 1 testing modeselect the TI input.Test-Enable Test-Input D TE TI CLK QQlogic symbol2-to-1 MUXfor circuit testing Sacn Flip-Flop（扫描触发器）Function Table (Fig. 7-22)20Edge-Triggered J-K
13、 Flip-Flop Characteristic EquationQ*=DI = JQ+KQJ K CLK Q QN0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 last QN last Q X X 0/1 last Q last QNFunction Table保持清 0置 1翻转保持DI（边沿触发式J-K触发器）logic symbol21Edge-Triggered J-K Flip-Flop DI（边沿触发式J-K触发器）Functional Behavior22T Flip-FlopA T (Toggle) flip-flop changes sta
14、te on every tick of the clock. (在每个时钟脉冲有效沿都会改变状态.)QQTTQOften used in counters and frequency dividers. （常用于计数器和分频器）Characteristic Equation: Q*=Q23 利用D触发器实现D：Q* = DT：Q* = QD = Q 利用J-K触发器实现JK：Q* = JQ + KQT：Q* = QJ = K = 1TQQND QCLK QTQQNJ Q CLK K Q1 利用D、J-K触发器实现T触发器240 1ENQ 维持Q 翻转Q*Function TableQQTENC
15、haracteristic Equation: Q*=ENQ+ENQ=ENQ T flip-flop with enable (具有使能端的T触发器)用D触发器实现用J-K触发器实现QQCLKTT触发器的另一种形式25不同类型触发器间的相互转换 D J-K, T J-K D, T T D, J-K关键：设计好转换逻辑电路。输入为转换后触发器的输入端及触发器的现态，输出为已有触发器的输入端。转换示意图：26J-K触发器：Q* = JQ + KQD触发器：Q* = D求转换逻辑电路：J=f(D,Q)，K=g(D,Q)若令J=D，K=D，则Q* = DQ + (D)Q= DQ + DQ=D不同类型触发器间的相互转换用J-K触发器实现D触发器27D触发器: QD* = D不同类型触发器间的相互转换用T触发器实现D触发器习题7.60 0 0 1 1 0 1 1Q DQD*0 1 0 1ENT0
