4052_CMOS_双4选1双向模拟开关

上传人:lizhe****0920 文档编号:47352637 上传时间:2018-07-01 格式:PDF 页数:12 大小:147.41KB
返回 下载 相关 举报
4052_CMOS_双4选1双向模拟开关_第1页
第1页 / 共12页
4052_CMOS_双4选1双向模拟开关_第2页
第2页 / 共12页
4052_CMOS_双4选1双向模拟开关_第3页
第3页 / 共12页
4052_CMOS_双4选1双向模拟开关_第4页
第4页 / 共12页
4052_CMOS_双4选1双向模拟开关_第5页
第5页 / 共12页
点击查看更多>>
资源描述

《4052_CMOS_双4选1双向模拟开关》由会员分享,可在线阅读,更多相关《4052_CMOS_双4选1双向模拟开关(12页珍藏版)》请在金锄头文库上搜索。

1、November 1983Revised January 1999CD4051BC CD4052BC CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demultiplexer 1999 Fairchild Semiconductor CorporationDSCD4051BC CD4052BC CD4053BC Single 8-Channel Analog

2、 Multiplexer/Demultiplexer Dual 4-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/DemultiplexerGeneral DescriptionThe CD4051BC, CD4052BC, and CD4053BC analog mul- tiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OF

3、F” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3 15V. For example, if VDD = 5V, VSS = 0V and VEE = 5V, analog sig- nals from 5V to +5V can be controlled by digital inputs of 0 5V. The multiplexer circuits dissipate extremely low qui- escen

4、t power over the full VDDVSS and VDDVEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input ter- minal all channels are “OFF”.CD4051BC is a single 8-channel multiplexer having three binary control inputs. A, B, and C, and a

5、n inhibit input. The three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output.CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be

6、turned on and connect the differential analog inputs to the differential outputs.CD4053BC is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole doubl

7、e-throw configu- ration.FeaturesI Wide range of digital and analog signal levels: digital 3 15V, analog to 15Vp-pI Low “ON” resistance: 80 (typ.) over entire 15Vp-p signal-input range for VDD VEE = 15VI High “OFF” resistance: channel leakage of 10 pA (typ.) at VDD VEE = 10VI Logic level conversion f

8、or digital addressing signals of 3 15V (VDD VSS = 3 15V) to switch analog signals to 15 Vp-p (VDD VEE = 15V)I Matched switch characteristics: RON = 5 (typ.) for VDD VEE = 15VI Very low quiescent power dissipation under all digital- control input and supply conditions: 1 W (typ.) at VDD VSS = VDD VEE

9、 = 10VI Binary address decoding on chipOrdering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Order NumberPackage NumberPackage DescriptionCD4051BCMM16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” NarrowCD4051B

10、CMTCMTC1616-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WideCD4051BCNN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WideCD4052BCMM16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” NarrowCD4052BCSJM16D16-Lead Small Outline Package

11、(SOP), EIAJ TYPE II, 5.3mm WideCD4052BCNN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WideCD4053BCMM16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” NarrowCD4053BCSJM16D16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WideCD4053BCNN16E16-Lead P

12、lastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wideh t t p :/w w w .e l e c f a n s .c o m 电子发烧友 h t t p :/b b s .e l e c f a n s .c o m 电子技术论坛2CD4051BC CD4052BC CD4053BCConnection DiagramsPin Assignments for DIP and SOICCD4051BCCD4052BCCD4053BCTruth Table*Dont Care condition.INPUT STATES“

13、ON” CHANNELSINHIBITCBACD4051BCD4052BCD4053B000000X, 0Ycx, bx, ax000111X, 1Ycx, bx, ay001022X, 2Ycx, by, ax001133X, 3Ycx, by, ay01004cy, bx, ax01015cy, bx, ay01106cy, by, ax01117cy, by, ay1*NONENONENONEh t t p :/w w w .e l e c f a n s .c o m 电子发烧友 h t t p :/b b s .e l e c f a n s .c o m 电子技术论坛CD4051B

14、C CD4052BC CD4053BC Logic DiagramsCD4051BCCD4052BCh t t p :/w w w .e l e c f a n s .c o m 电子发烧友 h t t p :/b b s .e l e c f a n s .c o m 电子技术论坛4CD4051BC CD4052BC CD4053BCLogic Diagrams (Continued) CD4053BCh t t p :/w w w .e l e c f a n s .c o m 电子发烧友 h t t p :/b b s .e l e c f a n s .c o m 电子技术论坛CD40

15、51BC CD4052BC CD4053BC Absolute Maximum Ratings(Note 1)Recommended Operating ConditionsNote 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The Electrical Characteristics tables provide conditions for actual device operation.DC Electrical Characteristics (Note 2)DC Supply Voltage (VDD)0.5 VDC to +18 VDCInput Voltage (VIN)0.5 VDC to VDD +0.5 VDCStorage TemperatureRange (TS)65C to +150CPower Dissipation

展开阅读全文
相关资源
相关搜索

当前位置:首页 > 学术论文 > 毕业论文

电脑版 |金锄头文库版权所有
经营许可证:蜀ICP备13022795号 | 川公网安备 51140202000112号