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1、?Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.Application Note 107 DS1020/DS1021 8Bit Programmable Delay LinesAPPLICATION NOTE 107072996 1/2
2、1 471INTRODUCTION This application note is designed to assist in the use of the DS1020/DS1021 programmable delay lines. The basic principles of device operation are covered in sim- plified form, but with sufficient detail to enable the user to understand what is happening within the device and how t
3、his affects its use in practical applications.These flexible devices can be configured as traditional delay lines, as pulse width modulators or even as pro- grammable oscillators. A variety of configurations are illustrated, the various features of which cover most applications.Some of the key consi
4、derations which must be taken into account when designing in these products, based on the experience of previous users of the devices, are also covered.The DS1020/DS1021 are similar devices, differing only in package and step size availability and response to power up conditions (see Page 107, Power
5、 Up).KEY PRODUCT FEATURES Programmable over 256 steps in increments of 0.15 to 2 ns (DS1020), 0.25 or 0.5 ns (DS1021)Guaranteed monotonicitySerial (3wire) or parallel (8bit) programmabilityCascadableDIP (DS1020 only) or SOIC packagingPRODUCT SELECTION (all times in ns)PART NUMBERSTEP ZERO DELAYDELAY
6、 PER STEPMAXIMUM DELAYDS1020015100.1548.25DS1020025 DS1021025100.2573.75DS1020050 DS1021050100.5137.50DS1020100101265.00DS1020200102520.00APPLICATION NOTE 107072996 2/21 472CIRCUIT CONFIGURATIONSProgrammable Delay LineDS1020/DS1021INPUTOUTPUTD CS EP0P7SERIAL DATACLKPARALLEL DATAENABLEMODE 1=PARALLEL
7、SELECT 0=SERIALTIMING WAVEFORMS Figure 1INPUTOUTPUTtDtDThis is the “normal” mode of operation for the DS1020/DS1021. Input pulses applied to the device reappear at the output after a delay time set by the device programming. Both leading and trailing edges of the input waveform are delayed by the sa
8、me amount.The delay time can be programmed either by means of a serial data input, or can be loaded into an 8bit parallel port. A Mode Select pin (S) determines which mode of operation is to be used. An Enable pin is available to latch in the serial data once it has been loaded, or to load parallel
9、data and isolate the device from further changes to a shared parallel bus.NOTE: In some of the following applications control and/or data input pins have been omitted for clarity. Unless reference is made to specific inputs, the same configuration can be used in either the serial or paral- lel mode.
10、Programmable Pulse WidthDS1020/DS1021P0P7INPUTOUTPUTOUTPUT WAVEFORMS Figure 2INPUTDS1020/DS1021OUTPUTThe DS1020/DS1021 can be combined with some sim- ple external logic to produce a programmable pulse width. In the example shown above the output pulse is triggered by the rising edge of the input wav
11、eform and can be adjusted in duration from 10 ns (the latent delay of the DS1020/DS1021) up to the maximum pro- grammed delay value.For correct operation over the full range of desired out- put pulse widths, the duration of both the high and low states of the input must be greater than the delay tim
12、e of the DS1020/DS1021 which corresponds to the maxi- mum output pulse width (see Page 108).The rising edge of the output will be delayed with respect to the input by the propagation delay through the two gates. The falling edge will be dependent on the programmed delay of the DS1020/DS1021 and the
13、propagation delay of the output gate (see diagram next page).APPLICATION NOTE 107072996 3/21 473INPUTINPUTDS1020/DS2021OUTPUTtPHLtDELAYtPHLtPLHtWTherefore the output pulse width is given by: tw = (input to falling edge of output) (input to rising edge of output)= (tDELAY + tPHL) (tPHL + tPLH) = tDEL
14、AY tPLHPULSE WIDTH MODULATOR Figure 3Figure 3 shows the range of pulse widths available for the various members of the DS1020/DS1021 family.NOTE: Using HCMOS gates the minimum pulse width will be approximately 5 ns.APPLICATION NOTE 107072996 4/21 474Programmable Oscillator If the output of the DS102
15、0/DS1021 is inverted and fed back to the input a freerunning oscillator is produced. The oscillator can be gated if desired by replacing the inverter with a NAND or NOR function and using the additional input as an enable.The period of the output signal will equal approximately twice the sum of the
16、programmed delay and the propa- gation delay through the inverter, or more accurately:fO = 1/ 2(tDELAY) DS1020 + (tPLH + tPHL)INVDS1020/DS1021P0P7OUTOUTPUT ININPUTOUTPUTtPHLtDELAYtDELAYtPLHThe minimum frequency is determined by the maximum achievable delay from the DS1020/DS1021, the maxi- mum is determined by the propagation delay of theinverter and the step zero delay time of the DS1020/DS1021.The following table summarizes some bench measurements on three
