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1、 TN00009 ADC design guidelines Rev. 1 8 May 2014 Technical note Document information Info Content Keywords ADC design guidelines Abstract This technical note provides common best practices for board layout required when Analog circuits (which are sensitive to digital noise) are combined with Digital
2、 circuits particularly when high-frequency or high- current circuits are involved NXP Semiconductors TN00009 ADC design guidelines TN00009 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved. Technical note Rev. 1 8 May 2014 2 of 10 Contact i
3、nformation For more information, please visit: http:/ For sales office addresses, please send an email to: Revision history Rev Date Description 1 20140508 Initial version. NXP Semiconductors TN00009 ADC design guidelines TN00009 All information provided in this document is subject to legal disclai
4、mers. NXP B.V. 2014. All rights reserved. Technical note Rev. 1 8 May 2014 3 of 10 1. Introduction The following Design Guidelines provide common best practice for board layout required when Analog circuits (which are sensitive to digital noise) are combined with Digital circuits particularly when h
5、igh-frequency or high-current circuits are involved. 1.1 Component placement Analog circuits should be separated from digital circuits to isolate them from switching noise. Noisy and high-frequency components should be located closer to the connectors/power supply. Fig 1. Recommended component place
6、ment 1.2 Ground strategy Use separate grounds for each domain (analog and digital) Use ground planes when possible If no ground plane is possible, use a “star” layout strategy for ground connections: Provide independent ground current returns when possible. Return paths can be shared (see U1 if sign
7、al traces need to be inserted on the ground plane side of the board, they should be as short as possible and perpendicular to the ground current return paths. Even when separate grounds are used for analog and digital domains, only one electrical point should be referred to as the system-wide ground
8、, i.e., both grounds should be connected together at a single point; this is commonly referred to as the chassis. A ferrite bead or inductor would work well for this connection while it will also decouple both circuits. 1.3 Bypass and decoupling capacitors A Bypass Capacitor offers a low impedance p
9、ath to high frequency current flow, reducing the noise current on power supply lines. Usually, a 0.1 uF capacitor will suffice and it should be as close to the device as possible. A Decoupling Capacitor provides isolation of two circuits; this will prevent noise from being transmitted from one circu
10、it to the other. It can be used with an inductor, forming a low pass filter. A 10 uF works well in these cases, and it should be connected close to the power supply. NXP Semiconductors TN00009 ADC design guidelines TN00009 All information provided in this document is subject to legal disclaimers. NX
11、P B.V. 2014. All rights reserved. Technical note Rev. 1 8 May 2014 5 of 10 Fig 3. Bypass and decoupling capacitors 1.4 Power planes A Power plane is desirable although is not as critical as a ground plane. For two-layer boards, the power plane can be replaced by wider traces (two or three times wide
12、r than other traces on the board). 1.5 Multi-layer boards Critical and/or complex designs would require Multi-Layer boards. In this case, its highly recommended to use different layers for ground and power planes. As many components are SMD (Surface Mounted Device), their connections need to be expo
13、sed on one of the external sides of the board (usually the top side), so internal layers can be dedicated to the power and ground planes, thus taking advantage from of the distributed capacitance. If more than four layers are used, higher speed signals can be shielded between the ground and power pl
14、anes. Slower signals can be routed on the outer layers. 1.6 Routing signals Do not overlap signals/power/ground from different domains (analog and digital). Otherwise, the distributed capacitance between the overlapping portions will couple high-speed digital noise into the analog circuitry. NXP Sem
15、iconductors TN00009 ADC design guidelines TN00009 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved. Technical note Rev. 1 8 May 2014 6 of 10 Fig 4. Routing signals Keep digital signals (especially high-frequency, noisy I/O or high-current)
16、 away from the analog signals. Even small capacitances between traces and planes could couple enough noise, not only for the fundamental frequency but also for the higher harmonics. High-impedance lines are the most sensitive to injected noise coupled through capacitance formed with close traces which have fast-changing voltages, such as digital clocks. In order to minimiz
