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1、Using Allegro PCB SI to Analyze a Boards Power Delivery System from Power Source to Die PadInternational Cadence Usergroup Conference September 15 17, 2003 Juergen Flamm, Cadence1CADENCE DESIGN SYSTEMS, INC.CADENCE CONFIDENTIALAbout the AuthorJuergen FlammSenior Technical Sales LeaderCadence Design
2、SystemsJuergen holds a MS EE degree from the “University Fridericiana” in Karlsruhe (Germany) Throughout his career, he has been actively involved at all levels and in all aspects of electronic design. He started designing wideband telephony line amplifiers and repeaters at AEG Telefunken. Next he j
3、oined Litef (Litton Germany) as the lead engineer for sensor electronic development. He designed mixed mode analog/digital ASICs, miniaturized hybrid electronics and next level multi-board system in a box electronics. He relocated to the United States in 1990 to join Litton corporate as the leader o
4、f an international technology transfer team. Shortly after, he was promoted to manager of the Analog Design Group to move on to manager of the Electronic Engineering Department. With the beginning of 2001, a planned careerr change brought Juergen to Cadence. He joined PSD as a Senior Technical Sales
5、 Leader with focus on the Allegro PCB SI family of tools.He holds 5 patents in the areas of performance electronics for fiber optic and MEMS sensors. 2CADENCE CONFIDENTIALAgenda Introduction Describing the problem Developing a Solution Step1:Power delivery system analysis for a board using Allegro P
6、CB PI Step2: Power delivery system analysis for a board/package combination using Allegro PCB SI SSN Step3: Combining Step1 and Step2 and more Summary Q & A3CADENCE CONFIDENTIALIntroduction Todays high speed circuits, operating at fast edge rates (100MHz), combined with decreasing supply voltage and
7、 increasing supply current demands, have been placing growing challenges on the design of power delivery systems. This presentation will show how Allegro PCB SI can be utilized to perform post-layout analysis of the power delivery system of a completed board design (see ICU 2003 paper #2 for details
8、). Post-layout analysis is only one use model of Allegro PCB SI. The tools real power will be experienced when also proactively employed for pre- layout design and analysis as well as for floor planning of a power delivery system. However, these use models are not subject of this presentation.4CADEN
9、CE CONFIDENTIALDescribing the ProblemExample:Parasitic elements in the PWR/GND supply path cause power supply noise and fluctuations on the chip supply rails5CADENCE CONFIDENTIALDescribing the Problem (cont.) Multiple elements must be considered simultaneously when analyzing a boards PWR/GND path fr
10、om power source to the chip supply rails. Board power source (VRM) Output current slew rate capability, dynamic source impedance, Board plane structures Differential and common mode impedance, resonances, Board decoupling capacitors Type, quantity, pin escape and via connections, placement location,
11、 - - - - - - - - - - - - - - - - - - - - Board traces and associated vias Interconnecting PWR/GND planes and chip package pins, Package model (chip) Pins, traces, planes, vias, bond wires, 6CADENCE CONFIDENTIALDeveloping a solution Step1 Analyze a boards PWR/GND plane pairs impedance, including deco
12、upling capacitors, using Allegro PCB PI frequency domain simulation. Step2 Analyze the PWR/GND connection path from planes to the chip power rails using Allegro PCB SI SSN time domain simulation. Step3 Append Step2 model with Step1 source impedance model. Use appended model and Allegro PCB SI SSN si
13、mulation to evaluate PWR/GND bounce impact on signal waveform and timing.7CADENCE CONFIDENTIALStep1 Allegro PCB PI Prepare board for and run Allegro PCB PI frequency domain simulations Complete Allegro PCB SI “Setup Advisor”, focus on “Identify DC Nets” Complete Allegro PCB PI “Setup Wizard”, select
14、 at least 1 standard library capacitor Use “Report” to identify capacitor types per plane pair Create/assign models for/to identified capacitor types Under “Cap Libraries” in Board Folder and select used capacitor types Approximate maximum worst case switching current, place noise source Determine V
15、RM model parameters and place VRM Set preferences and run multi node simulations Analyze resulting impedance graphs Optionally determine a simple worst case source impedance model (R, L, C)8CADENCE CONFIDENTIALStep1 Design & AnalysisReport Library Setup9CADENCE CONFIDENTIALStep1Board with highlighted Plane Shapes, VRM, Noise Source, Grid Size 10CADENCE CONFIDENTIALStep1Multi Node Simulation resultSimple source impedance approximation: Z = 40mOhm + j2pi*f*0.32nH11CADENCE CONFIDENTIALStep2 Allegro PCB SI -SSN Prepare board for and run Allegro
