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1、第4章 数字I/O模块 2、要求、要求 了解端口输入输出电路了解端口输入输出电路 掌握掌握MSP430单片机数字单片机数字I/O模块的模块的特点与配置方法。特点与配置方法。 掌握掌握MSP430单片机数字单片机数字I/O模块按模块按键、键、LED接口方法。接口方法。 1、内容、内容 数字数字I/O模块概述模块概述 数字数字I/O模块寄存器设置模块寄存器设置 端口输入输出电路端口输入输出电路 端口功能端口功能 寄存器与控制位寄存器与控制位 数字数字I/O端口应用端口应用 习题习题 The digital I/O features include: Independently programmab
2、le individual I/Os Any combination of input or output Individually configurable P1 and P2 interrupts. Independent input and output data registers Individually configurable pullup or pulldown resistors MSP430系列具有高达系列具有高达12组数字组数字I/O端口端口 (P1 to P11 and PJ). 大部分端口有大部分端口有8个个I/O线。线。 Each I/O line is indiv
3、idually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors, as well as, configurable drive strength, full or reduced. PJ contains only 4 I/O lines. Ports P1 and P2 always have interrupt
4、 capability. Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. 所有所有P1口口I/O线共用一个中断矢量线共用一个中断矢量 P1IV，所有所有P2口口I/O线共用一个中断矢量线共用一个中断矢量 P2IV。On some devices, additional ports with interrupt capability
5、 may be available and contain their own respective interrupt vectors. 1 Digital I/O Module 1 1 数字数字I/OI/O模块概述模块概述 Individual ports can be accessed as byte-wide ports or can be combined into word-wide ports and accessed via word formats. Port pairs P1 and P2, P3 and P4, P5 and P6, and so on, are asso
6、ciated with the names PA, PB, PC, and so on, respectively. All port registers are handled in this manner with this naming convention except for the interrupt vector registers; for example, PAIV does not exist for P1IV and P2IV. When writing to port PA with word operations, all 16 bits are written to
7、 the port. When writing to the lower byte of the PA port using byte operations, the upper byte remains unchanged. Similarly, writing to the upper byte of the PA port using byte instructions leaves the lower byte unchanged. When writing to a port that contains less than the maximum number of bits pos
8、sible, the unused bits are a “dont care“. Ports PB, PC, PD, PE, and PF behave similarly. Reading of the PA port using word operations causes all 16 bits to be transferred to the destination. Reading the lower or upper byte of the PA port (P1 or P2) and storing to memory using byte operations causes
9、only the lower or upper byte to be transferred to the destination, respectively. Reading of the PA port and storing to a general-purpose register using byte operations causes the byte transferred to be written to the least significant byte of the register. The upper significant byte of the destinati
10、on register is cleared automatically. Ports PB, PC, PD, PE, and PF behave similarly. When reading from ports that contain less than the maximum bits possible, unused bits are read as zeros (similarly for port PJ). (1) Input Registers (PxIN) Each bit in each PxIN register reflects the value of the in
11、put signal at the corresponding I/O pin when the pin is configured as I/O function. These registers are read only. Bit=0: Input is low Bit=1:Input is high (2) Output Registers (PxOUT) Each bit in each PxOUT register is the value to be output on the corresponding I/O pin when the pin is configured as
12、 I/O function, output direction. Bit=0: Output is low Bit=1:Output is high If the pin is configured as I/O function, input direction and the pullup/pulldown resistor are enabled, the corresponding bit in the PxOUT register selects pullup or pulldown. Bit=0: Pin is pulled down Bit=1:Pin is pulled up
13、2 Digital I/O Operation 2 2 数字数字I/OI/O模块寄存器设置模块寄存器设置 (3) Direction Registers (PxDlR) Each bit in each PxDIR register selects the direction of the corresponding I/O pin, regardless of the selected function for the pin. PxDIR bits for I/O pins that are selected for other functions must be set as requi
14、red by the other function. Bit=0: Port pin is switched to input direction Bit=1:Port pin is switched to output direction (4) Pullup or Pulldown Resistor Enable Registers (PxREN) PxREN的各位用于使能对应的各位用于使能对应I/O引脚的上拉引脚的上拉/下拉电阻，该寄存器需和下拉电阻，该寄存器需和PxDlR 、PxOUT配合使配合使 用，才能完成上拉用，才能完成上拉/下拉的配置下拉的配置. Bit=0: Pullup/p
15、ulldown resistor disabled Bit=1:Pullup/pulldown resistor enabled Table 12-1 summarizes the usage of PxDIR, PxREN, and PxOUT for proper I/O configuration. (5) Output Drive Strength Registers (PxDS) Each bit in each PxDS register selects either full drive or reduced drive strength. Default is reduced
16、drive strength. Bit=0: Reduced drive strength Bit=1:Full drive strength NOTE: All outputs default to reduced drive strength to reduce EMI. Using full drive strength can result in increased EMI. (6) Function Select Registers (PxSEL) Each PxSEL bit is used to select the pin function - I/O port or peripheral module function. Bit=0: I/O Function is selected for the pin Bit=1: Peripheral module function
