《电子钟时间设定和显示程序》由会员分享，可在线阅读，更多相关《电子钟时间设定和显示程序（15页珍藏版）》请在金锄头文库上搜索。
1、 实验名称实验名称：电子钟时间设计实验目的实验目的：实验设备实验设备：实验原理实验原理： 这个电子钟电路分成四个模块方式来讨论： 七段显示器电路设计 电子钟时间计数 End Block SEVEN_SEGMENT;Debounce : Block- Timer Key Debounce SIGNAL D0, D1, S, R,DLY,NDLY : STD_LOGIC; Begin Process (CPN) Begin IF CPNEVENT AND CPN=1 THEN IF SAMPLE = 1 THEN D1 = D0; D0 = Key(2);-二级延迟 S = D0 AND D1;
2、R = NOT D0 AND NOT D1; END IF; END IF; End Process;DLY = R NOR NDLY;-RS 触发器 NDLY =S NOR DLY; DLY_OUT = DLY;-RS 触发器输出 End Block Debounce;Differential : Block Signal D1,D0 : STD_LOGIC; BEGIN Process (CPN) Begin IF CPNEVENT AND CPN=1 THEN D1 = D0; D0 = DLY_OUT;-二级延迟 END IF; End Process; DIFF = D0 AND N
3、OT D1;-微分 END Block Differential;TimerSet : Block-Sec Signal SET,EC : STD_LOGIC; Begin Process (CPN) Begin IF SET = 1 THEN Q = “011“; ELSIF CPNevent AND CPN=1 THEN IF EC =1 THEN Q = Q-1; END IF; END IF; End Process;SET = 1 WHEN Q=7 ELSE 0; EC = DIFF AND Key(2);- TIMER KEY 微分 STATE = Q(1 DOWNTO 0);-
4、Record Timer State End Block TimerSet;END a;除 60 计数程序如下LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY COUNTER60 IS PORT( CP : IN STD_LOGIC;-时钟脉冲 BIN : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);-二进制 S : IN STD_LOGIC;-输出启动信号 CLR : IN STD_LOGIC
5、;-清除信号 EC : IN STD_LOGIC;-使能计数信号 CY60 : OUT STD_LOGIC-计数 60 进位信号 ); END COUNTER60;-*ARCHITECTURE a OF COUNTER60 IS SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0) ; SIGNAL RST, DLY : STD_LOGIC; BEGINPROCESS (CP,RST)- 计数 60 BEGIN IF RST = 1 THEN Q = “000000“;- 复位计数器 ELSIF CPevent AND CP = 1 THEN DLY = Q(5);
6、 IF EC = 1 THEN Q = Q+1;- 计数值加 1 END IF; END IF; END PROCESS;CY60 = NOT Q(5) AND DLY;- 进位信号微分 RST = 1 WHEN Q=60 OR CLR=1 ELSE- 复位信号设定 0; BIN = Q WHEN S = 1 ELSE- 计数输出 “000000“; END a;除 24 计数程序如下LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;-
7、*ENTITY COUNTER24 IS PORT( CP : IN STD_LOGIC;-时钟脉冲 BIN : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);-二进制 S : IN STD_LOGIC;-输出启动信号 CLR : IN STD_LOGIC;-清除信号 EC : IN STD_LOGIC;-使能计数信号 CY24 : OUT STD_LOGIC-计数 24 进位信号 ); END COUNTER24;-*ARCHITECTURE a OF COUNTER24 IS SIGNAL Q : STD_LOGIC_VECTOR (4 DOWNTO 0) ; SIGNAL RST, DLY : STD_LOGIC; BEGINPROCESS (CP,RST)- 计数 24 BEGIN IF RST = 1 THEN Q = “00000“;- 复位计数器 ELSIF CPevent AND CP = 1 THEN DLY = Q(4); IF EC = 1 THEN Q = Q+1;- 计数值加 1 END IF; END IF; END PROCESS;CY24 = NOT Q(4) AND DLY;- 进位信号微分 RST = 1 WHEN Q=24 OR CLR=1 ELSE- 复位信号设定 0;BIN = (0 END a;
