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1、11Instruction Set Principles Introduction Classifying Instruction Set Architectures Addressing Modes Type and Size of Operands Operations in the Instruction Set Instructions for Control Flow Instruction Format The Role of Compilers The MIPS Architecture ConclusionCDA 5155 Spring 2012Copyright 2012 P
2、rabhat Mishra2IntroductionAn instruction set architecture is a specification of a standardized programmer-visible interface to hardware.A set of instructionsWith associated argument fields, assembly syntax, and machine encoding.A set of named storage locationsRegisters, memory.A set of addressing mo
3、desWays to name locations3Classifying ArchitecturesClassification is based on addressing modes.Stack architectureOperands implicitly on top of a stack. Accumulator architectureOne operand is implicitly an accumulatorGeneral-purpose register architectureRegister-memory architecturesOne operand can be
4、 memory.Load-store architecturesAll operands are registers (except for load/store)4Four Architecture ClassesAssembly for C:=A+B25Classification based on Operands# of Memory Operands# of OperandsType of ArchitectureExamples03Register-registerAlpha, ARM, MIPS, PowerPC, Sparc12Register-memoryIntel 80x8
5、6, Motorola 68000, TI C54x22Memory-memoryVAX33Memory-memoryVAX Instruction-set architecture can also be classified based on the number of operands2-operand and 3-operand Further classification can be done based on the type of operands6Comparison of Architecture TypesTypeInstruction EncodingCode Gene
6、ration# of Clock Cycles/Inst.Code SizeRegister- registerFixed-lengthSimpleSimilarLargeRegister- memoryEasyModerateDifferentMediumMemory- memoryVariable-lengthComplexLarge variationCompactAdvantages Disadvantages7Endians carry disabled at word boundaries.SIMD: Single Instruction Multiple DataMultimed
7、ia instructions exploit the fact thatMany registers, adders etc. are wide (32/64 bit)Most multimedia data types are narrow e.g., 8 bit per color, 16 bit per audio sample per channel 2-8 values can be stored/register and added.19HP precision architecture (hp PA)Half word add instruction HADD:Optional
8、 saturating arithmetic. Up to 10 instructions can be replaced by HADD.Half word add?20Instructions for Control FlowFour basic types:Conditional branchesJumps (unconditional)Procedure callsProcedure returnsSPEC CPU2000 on Alpha621Addressing Modes for Control FlowPC-relative (PC + displacement)Target
9、is known at compile time.Position independence (relocatable)Register indirect jumps (register has address)Procedure returnsCase / switch statementsVirtual functions or methodsHigh-order functions or function pointersDynamically shared libraries22Branch Distance DistributionSPEC CPU2000 on Alpha 2003
10、 Elsevier Science (USA). All rights reserved.23Conditional Branch Options Condition Code (CC) RegisterFor example: X86, ARM, PowerPC, SPARC, ALU operations set condition code flags in the CCRBranch just checks the flag Condition registerFor example: Alpha, MIPSComparison instruction puts result in a
11、 GPRBranch instruction checks the register Compare temp = vk; vk = vk+1; vk+1 = temp;) Assembly language program (for MIPS) swap:sll$2, $5, 2 add$2, $4,$2 lw$15, 0($2) lw$16, 4($2) sw$16, 0($2) sw$15, 4($2) jr$31 Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010
12、 0001000000100000 . . .C compilerassembler28Compiler Structure829Compiler OptimizationsN.M. Not Measured30Compiler OptimizationsN.M. Not Measured31Phase Ordering ProblemIt is difficult to decide the sequence of compiler steps to generate optimal codeExample: Consider interaction between two stepsCom
13、mon sub-expression eliminationR = a + b c + d x (g + b c) Needs temporary to store the valueRegister allocationAssigning registers to variables and temporaries It is typically done towards the end.Depending on register pressure, it is profitable to recompute certain expressions than holding a regist
14、er for long (generates memory spills). 32Effect of Compiler Optimization 2003 Elsevier Science (USA). All rights reserved.933Architectural Support for CompilerProvide regularityOrthogonality (independence) of:Registers usedAddressing modesOperations usedProvide primitives, not solutionsDont directly
15、 support specific kernels or languagesSimplify trade-offs among alternativesGenerate efficient code sequence at compile timeDont interpret values known at compile time 34Putting It All Together Use GPRs with load-store architecture Support simple addressing modesDisplacement (12-16), immediate (8-16
16、), register indirect Support basic types8-, 16-, 32-, 64-bit integers and 64-bit floats Support most executed operationsLoad, store, add, subtract, move, and shiftCompare equal/not equal/less, branch (PC-relative) with at least 8 bits, jump, call, and return Instruction encoding based on goalFixed encoding for performance and variable for code size
