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1、1FN8222.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 20
2、05. All Rights Reserved All other trademarks mentioned are the property of their respective owners.X9C102, X9C103, X9C104, X9C503Digitally Controlled Potentiometer (XDCP)FEATURES Solid-state potentiometer 3-wire serial interface 100 wiper tap points Wiper position stored in nonvolatile memory and re
3、called on power-up 99 resistive elements Temperature compensated End to end resistance, 20% Terminal voltages, 5V Low power CMOS VCC = 5V Active current, 3mA max. Standby current, 750A max. High reliability Endurance, 100,000 data changes per bit Register data retention, 100 years X9C102 = 1k X9C103
4、 = 10k X9C503 = 50k X9C104 = 100k Packages 8-lead SOIC and DIP Pb-free plus anneal available (RoHS compliant)DESCRIPTIONThe X9Cxxx are Intersil digitally controlled (XDCP) potentiometers. The device consists of a resistor array, wiper switches, a control section, and nonvola- tile memory. The wiper
5、position is controlled by a three-wire interface.The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switch- ing network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is contro
6、lled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation.The device can be used as a three-terminal potentiom- eter or as a two-terminal variable resistor in a wide variety of applications including:
7、control parameter adjustments signal processingBLOCK DIAGRAMUp/Down(INC)IncrementDevice(U/D)(CS)VCC (Supply Voltage)VSS (Ground)7-Bit Up/Down Counter7-Bit Nonvolatile MemoryStore and Recall Control CircuitryOne ofHundred DecoderResistor ArrayU/D INC CSTransferVCC GNDOne- Gates99989796210Control and
8、MemoryGeneralDetailedRL/VL RW/VWRH/VHVH/RHRW/VWVL/RLSelectData SheetSeptember 19, 20052FN8222.1 September 19, 2005PIN CONFIGURATIONVCCCSVL/RLVW/RWINCU/DVSS12348765VH/RHX9C102/103/104/503DIP/SOICORDERING INFORMATIONPART NUMBERPART MARKINGRTOTAL (k)TEMPERATURE RANGE (C)PACKAGEX9C102PX9C102P10 to 708 L
9、d PDIPX9C102PZ (Note)X9C102P Z0 to 708 Ld PDIP (Pb-free)X9C102PIX9C102P I-40 to 858 Ld PDIPX9C102PIZ (Note)X9C102P Z I-40 to 858 Ld PDIP (Pb-free)X9C102S*X9C102S0 to 708 Ld SOICX9C102SZ* (Note)X9C102S Z0 to 708 Ld SOIC (Pb-free)X9C102SI*X9C102S I-40 to 858 Ld SOICX9C102SIZ* (Note)X9C102S Z I-40 to 8
10、58 Ld SOIC (Pb-free)X9C103PX9C103P100 to 708 Ld PDIPX9C103PZ (Note)X9C103P Z0 to 708 Ld PDIP (Pb-free)X9C103PIX9C103P I-40 to 858 Ld PDIPX9C103PIZ (Note)X9C103P Z I-40 to 858 Ld PDIP (Pb-free)X9C103S*X9C103S0 to 708 Ld SOICX9C103SZ* (Note)X9C103S Z0 to 708 Ld SOIC (Pb-free)X9C103SI*X9C103S I-40 to 8
11、58 Ld SOICX9C103SIZ* (Note)X9C103S Z I-40 to 858 Ld SOIC (Pb-free)X9C503PX9C503P500 to 708 Ld PDIPX9C503PZ (Note)X9C503P Z0 to 708 Ld PDIP (Pb-free)X9C503PIX9C503P I-40 to 858 Ld PDIPX9C503PIZ (Note)X9C503P Z I-40 to 858 Ld PDIP (Pb-free)X9C503S*X9C503S0 to 708 Ld SOICX9C503SZ* (Note)X9C503S Z0 to 7
12、08 Ld SOIC (Pb-free)X9C503SI*X9C503S I-40 to 858 Ld SOICX9C503SIZ* (Note)X9C503S Z I-40 to 858 Ld SOIC (Pb-free)X9C104PX9C104P1000 to 708 Ld PDIPX9C104P-30 to 708 Ld PDIPX9C104PIX9C104P I-40 to 858 Ld PDIPX9C104PIZ (Note)X9C104P Z I-40 to 858 Ld PDIP (Pb-free)X9C104S*X9C104S0 to 708 Ld SOICX9C104SZ*
13、 (Note)X9C104S Z0 to 708 Ld SOIC (Pb-free)X9C104SI*X9C104S I-40 to 858 Ld SOICX9C104SI-Z-40 to 858 Ld SOICX9C104SIZ* (Note)-40 to 858 Ld SOIC (Pb-free)NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate ter
14、mination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.*Add “T1“ suffix for tape and reel.X9C102, X9
15、C103, X9C104, X9C5033FN8222.1 September 19, 2005PIN DESCRIPTIONSPinSymbolBrief Description1INCIncrement . The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input.2U/DUp/Dow
16、n. The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented.3RH/VHRH/VH. The high (VH/RH) terminals of the X9C102/103/104/503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the
