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1、上海交通大学 硕士学位论文 DSP3000的研究与实现前端设计与验证 姓名：李宇飞 申请学位级别：硕士 专业：计算机系统结构 指导教师：陈进 20040116 DSP3000 DSP RTL RTL RTL DSP RTL RTL RTL DSP DSP3000 RTL DSP3000 RTL RTL DSP3000 RTL RTL DSP3000 DSP3000 : RTL 4 / 64 Research and Implementation for DSP3000 Front-end Design and Verification Abstract In the field of IC d
2、esign based on the top-down design method, great challenges have been imposed on front-end design, architecture, RTL modeling and verification. The designers are r equired to be equipped with not only the ability to grasp the processor structure on the algorithm level but also to predict issues enco
3、untered in physical implementation, which is critical to the convergence of the design. This dissertation discusses optimization ideas on the aspects of system architecture, RTL modeling as well as RTL testing. Great efforts are focused on the design and analysis of DSP control structure, RTL model
4、implementation and RTL model verification. This paper also emphasizes on the optimization of the model and the tradeoff between circuit complexity and performance. 5 / 64 This paper is organized according to the structure from high level to low level design. The organization follows the sequence of
5、front-end design flow, which includes the fundamental introduction, processor structure design, RTL technology, front-end verification. The first chapter introduces the basic concepts and knowledge on the DSP structure design, which discusses the design ideas on memory structure, pipeline, instructi
6、on set and ALU (Arithmetic Logic Unit). Substantial literatures and cases from industry are quoted to explain the tradeoff between the performance and cost. The design of this DSP is inspired by the ideas from some of these cases. The second chapter discusses a quantitative approach for the research
7、 of memory structure, pipeline and instruction set. It also introduces a method of pipeline optimization, a parallel structure as well as a control flow design. The pipeline optimization, memory structure for DSP3000 and the design for control flow are discussed in the second, the third and the fort
8、h section respectively. Besides, special effort is paid to illustrate an optimized design for the stack-based loop instruction. 6 / 64 The third chapter covers the topic on the implementation of RTL model, which is divided into the logic modeling skills and the physical modeling skills. Due to the c
9、omplexity of DSP3000s, the RTL code cited in this chapter is mainly extracted from the simplified RTL model of DSP3000. Chapter four focuses on the issue of RTL testing. A test methodology is presented, which is easier to implement and manage comparing to the traditional test methods. Chapter five summarizes the performance of DSP300 and the test results of some application programs on DSP3000. Key words : RTL, pipeline, memory, control flow
