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1、哈尔滨理工大学学士学位论文- I -定时器的设计与实现摘要伴随着当今信息和自动化技术的发展，数字控制技术广泛应用于工业生产当中，计算机控制中常需要定时的数据读取、信号输出、和屏幕刷新等操作，特别是精度要求高的控制系统和数据采集系统，更要求精确的定时操作。因此必须采用一种新的定时器设计方法来代替传统的定时器设计方法，以更好地满足系统的高精度定时要求。本文工作重点在于结合松下公司的需求，进行定时器的整体设计和各子模块的具体实现。本文首先介绍课题背景、意义、国内外定时器及芯片设计的现状及内容。阐述 VerilogHDL 语言、 APB 总线和 Modelsim 工具的相关知识。其次，研究和分析传统定
2、时器的原理，结合定时精度的需求，提出一种合理的定时器设计方案，包括定时器的总体设计方案、定时器的各模块设计方案。基于该设计方案，用 VerilogHDL 语言实现定时器各模块的功能。其中定时器的核心模块包含前置分频器、轻功能定时器组和多功能定时器。在实现轻功能定时器组时，对其级联功能进行改进和优化，使其结构更紧凑，灵活性更高。最后基于 Modelsim 进行功能仿真，通过对波形的分析，得出该定时器能很好地满足客户需求。关键词 定时精度；数据读取；级联；数据捕获哈尔滨理工大学学士学位论文- II -The design and implementation of timer AbstractAl
3、ong with todays information and automation technology, digital control technology is widely used in industrial production, the computer-controlled often needs read data by definite time, the definite time signal output, and definite time screen refresh operation, etc., especially in high-precision c
4、ontrol systems and data acquisition systems, more precise timing requirements of the operation. It is necessary to adopt a new design method of the timer to replace the traditional design methods to be better meet with the system requirements of high precision timing. This paper focuses on the work
5、of combining the needs of Panasonic company, the overall design of the timer and the concrete realization of sub-modules. Firstly, the subject of the background, significance, the quo of timer and the chips designing both at home and abroad is introduced in this thesis. Expound in VerilogHDL languag
6、e, APB bus and the relevant knowledge about Modelsim tools. Secondly, according to the research and analysis of the principles of traditional timer, combined with the demand for precision timing, give out a reasonable timer design, including the overall design, the timer modules design. Based on the
7、 design ,use VerilogHDL to implement the functions of the timer modules. The timer core modules include pre-divider timer , light-function timer group and multi-function timer. Along with the implementation of the light-function timer group, some improvements and optimizations have been done in this
8、 thesis.According to the improvement and optimization, its structure is more compact, and has a higher flexibility.Finally, based on the Modelsim tools functional simulation and waveform analysis of the timer, the timer can be very well content with the customers needs. 哈尔滨理工大学学士学位论文- III -Keywords
9、timing accuracy; data read; cascade; data capture哈尔滨理工大学学士学位论文- IV -目录摘要 .IAbstract.II第 1 章 绪论 .11.1 课题背景及意义 .11.2 国内外研究现状 .21.3 主要研究内容 .4第 2 章 相关知识介绍 .52.1 Verilog HDL 语言简介 .52.2 APB 总线简介 .52.3 Modelsim 工具简介 .72.4 本章小结 .8第 3 章 定时器的总体设计 .93.1 框架设计 .93.1.1 端口分类 .93.1.2 信号列表 .93.2 定时器内部的模块划分 .103.3 定时器各功能模块的设计及功能描述 .113.3.1 前置分频器 .113.3.2 轻功能定时器组 .123.3.3 多功能定时器 .133.4 本章小结 .15第 4 章 定时器的各模块实现 .164.1 前置分频器 .164.1.1 功能描述及时序分析 .164.1.2 工作模式图 .
