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1、硕士学位论文低功耗 SoC 后端设计中几个关键技术的研究SOME KEY TECHNOLOGIES OF SoCIN BACK-END DESIGN侯春风哈尔滨工业大学2009 年 12 月国内图书分类号：TM431.2 学校代码：10213国际图书分类号：621.3 密级：公开硕士学位论文低功耗 SoC 后端设计中几个关键技术的研究硕 士 研 究 生 ： 侯春风导 师： 王明江教授申 请 学 位： 工学硕士学 科 专 业： 微电子学与固体电子学所 在 单 位： 深圳研究生院答 辩 日 期： 2009 年 12 月授予学位单位： 哈尔滨工业大学Classified Index: TM431.2
2、U.D.C: 621.3Dissertation for the Master Degree in EngineeringSOME KEY TECHNOLOGIES OF SoCIN BACK-END DESIGNCandidate:Supervisor:Academic Degree Applied for:Specialty:Affiliation:Date of Defence:Degree-Conferring-Institution:Hou ChunfengProf.Wang MingjiangMaster of EngineeringMicroelectronics and Sol
3、id-StateElectronicsShenzhen Graduate SchoolDecember, 2009Harbin Institute of Technology哈尔滨工业大学工学硕士学位论文摘 要随着工艺水平的不断发展，集成电路已经进入超深亚微米的 SoC 时代，设计规模越来越大，单一 SoC 芯片的集成度已经达到了上亿门。然而，发展的同时也带来了新的挑战。一方面，由于电路工作频率的要求越来越高，由此带来的功耗问题已经成为新一代 SoC 设计方法学的重要研究内容；另一方面，集成度的提高，给测试矢量的生成带来了更多的挑战，有效地测试 SoC芯片变得更加困难，因而，必须采用有效的可测
4、性设计技术，提高测试覆盖率，确保设计质量。本文主要研究了低功耗 SoC 后端设计中的布局布线技术、后端低功耗设计方法、可测性设计方法等，并以一颗 G.722.2 语音 SoC 为例，将上述研究成果完成了实践。论文首先研究了 CMOS 电路的主要功耗来源，研究了低功耗设计技术的理论及实现方法。通过对 G.722.2 语音 SoC 进行功耗分析，了解总体功耗分布，分别采用门控时钟、操作数隔离、存储器分块访问等不同的低功耗技术有针对性的进行了低功耗设计，成功地实现了降低功耗的目的。论文研究了 DFT 技术以及测试矢量生成技术。论文使用 DFT Compiler 工具 ， 采 用 扫 描 测 试 技
5、术 对 G.722.2 语 音 SoC 实 现 了 可 测 性 设 计 ， 并 运 用TetraMAX 完成测试矢量的生成。通过静态时序分析和形式验证保证了设计在时序和功能上的双重可靠性。论文研究了后端布局布线技术以及信号完整性的相关理论。论文使用 SoCEncounter 完成了 G.722.2 语音 SoC 物理设计，包括布局布线，电源规划，时钟树综合以及详细布局布线，设计规则验证，同时，还借助工具对设计进行了串扰分析，IR drop 分析，最终得到了功能完备，时序正确的可靠性设计，成功地得到了用于投片的 GDSII 版图数据。关键词：低功耗；可测性；扫描；布局布线- I -哈尔滨工业大学
6、工学硕士学位论文AbstractWith the continuous development of technology, integrated circuits has enteredthe ultra-deep sub-micron era of SoC, the scale of design is becoming more andmore large, single-chip SoC integration has also reached millions gates. However,development has also brought new challenges. On
7、 the one hand, because thedemand of circuit operating frequency has become more and more high, and theresulting power consumption issues must be the important content of a newgeneration SoC design methodology; the other hand, the raise of integration hasbrought additional challenges to the test vect
8、or generation, effectively testing to SoCchips become more difficult, therefore, we must adopt some DFT technology toimprove test coverage rate, to ensure design quality. This paper mainly studiesbackend low-power SoC designs in the layout and routing technology, back-endlow-power design methodology
9、, design for testability methods, and brings theresearch results into practice through an example of G.722.2 speech SoC.This paper firstly analyzes the main power source of CMOS circuits, studiesthe theory of low-power design techniques and implementation methods in detail.We learn that general powe
10、r distribution of G.722.2 speech SoC through doingpower analysis on it. Then, use different low-power techniques such as clock gating,operand isolation, memory block access to different parts of the design, andsuccessfully achieve the purpose of reducing power consumption.The paper studies DFT techn
11、iques and test vector generation techniques. Thispaper adapt some scan test techniques to complete the DFT design of G.722.2speech SoC with DFT Compiler, and complete the test vector generation using withTetraMAX. By static timing analysis and formality verification to G.722.2 speechSoC, we ensure t
12、hat the designs function and timing are both reliability.The paper studies backend layout, routing technology and related theories ofsignal integrity. Physical design of G.722.2 speech SoC has been completed withSoC Encounter, including place and route, power supply planning, clock treesynthesize an
13、d detailed layout, design rule verification and so on. Then, to ensurethe design can meet the demand of signal integrity, we also do cross-talk analysisand IR drop analysis, achieve the fully functional, timing correct reliability design,and obtain the GDSII layout data which should be used to tape out.Keywords: low-power, DFT, scan, place and route- II -哈尔滨工业大学工学硕士学位论文目 录摘要. IAbstract. II第 1 章 绪 论 . 11.1 课题背景 . 11.2 研究目的和意义 . 21.3 本文主要研究内容和结构安排. 3第 2 章 SoC 低功耗设计. 52.1 CMOS 集成电路功耗的来源. 52.1.1 动态功耗 .
