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1、SAP-1 Cpu 电路设计,一.SAP-1 CPU及计算机的组成架构简介 二.SAP-1 CPU指令.寻址法.程序设计 三.16*8的ROM设计与仿真 四 .SAP-1 CPU设计与仿真,实验目的:,实验原理,小组成员,薛宝(20054440118) 汪威(20054440119) 高亮(20054440120) 吴安乐(2005444021) 陆仁聪(20054440122) 谢素斌(20054440123) 吴运兴(20054440124) 江宪清(20054440126),一.SAP-1 CPU及计算机的组成架构简介,所有寄存器是以三态(three state)输出方式,连接至webu
2、s上。虽然现在不是使用传统TTL电路组成,而是使用CPLD -state type declare SIGNAL PState :STATE; -present state SIGNAL NState :STATE; -next state BEGIN .* ChangeStateMode:PROCESS(CR,RST) -state s0s5 BEGIN IF RST=1THEN -reset cpu PC =“0000”; -pogram counter=0H ACC=“00000000”; -accumulator=0H RUN =1; -CPU run program enable P
3、State=S0; -Initial cpu present state ELSIF CPEVENT AND CP =0THEN -clock negative edage,IF RUN =1THEN -run program eanble? CASE PState IS -check cpu present state WHEN S0= -(address state ,2.编写“指令捕捉周期(fetch cycle)即状态S0S2的命令,Changestatemode:process(cp,rst) -state s0s5 variable flag,f1:boolean; begin i
4、f rst =1 then . Pstate nstate nstate =s2; if flag=ture then pc =pc+1; flag:=false; end if;,When s2= Nastate End case; ,3.编写”指令执行周期(fetch cycle)”,即状态S3S5的命令,首先在Case When语句的状态S3处,加入下面粗体字命令,将“指令寄存器” (IR)截取高4位指令至TMP里 Elsif cpevent and cp=0 then when s2= When s3= nstate ,其余指令执行周期的命令,不放入CASE WHEN语句里,而改以IF
5、-ELSE将状态S3S5命令独立出来,这么作只是不希望CASE WHEN语句太过冗长。 changestatemode : process(cp,rst) variable flag, F1:boolean; Begin If rst =1 then Elsif cpevent and cp=0 then If run=1then case pstate is when s0= nstate=s1; end case; pstate=nstate; End if;,If pstate =s3 then If(tmp=“0000”)or(tmp=“0001”)or(tmp=“0010”)then
6、 Mar=ir(3 downto 0); elsif tmp =“1110”then outreg=acc; elsif tmp =“1111”then run=0; End if Elsif pstate=s4 then if tmp=“0000”then acc=databus; elsif tmp=“0001”then breg=databus; elsif tmp=“0010”then breg=databus; end if; Elsif pstate=s5 then if tmp =“0001”and f1=ture then Num =unsigned(acc)+unsigend(breg);,Acc =std_logic_vector(num); F1:=false; Elsif tmp=“0010” and f1 =true then num =unsigned(acc)-unsigned(breg); Acc=std_logic_vector(num); F1:false; End if; End if; End if; End process changestatemode;,连接,演讲完毕,谢谢观看!,