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1、 问答：Point out design objects in the figure such as :design, cell, reference, port, pin, net, then write a command to set 5 to net ADesign: topReference: ADD DFFCell: U1 U2Port: A B clk sumPin: A B D QNet: A B SINSet_load 5 get_nets Awhy do we not choose to operate all our digital circuits at these l
2、ow supply voltages? 答：1）不加区分地降低电源电压虽然对减少能耗能正面影响，但它绝对会使门的延时加大2）一旦电源电压和本征电压（阈值电压）变得可比拟，DC 特性对器件参数（如晶体管阈值）的变化就变得越来越敏感3）降低电源电压意味着减少信号摆幅。虽然这通常可以帮助减少系统的内部噪声（如串扰引起的噪声），但它也使设计对并不减少的外部噪声源更加敏感）问道题：1. CMOS 静态电路中，上拉网络为什么用 PMOS,下拉网络为什么用 NMOS 管2. 什么是亚阈值电流，当减少 VT 时，V GS =0 时的亚阈值电流是增加还是减少？3. 什么是速度饱和效应4. CMOS 电压越低，功
3、耗就越少？是不是数字电路电源电压越低越好，为什么？5. 如何减少门的传输延迟？ P2036. CMOS 电路中有哪些类型的功耗？7. 什么是衬垫偏置效应。8. gate-to-channel capacitance CGC,包括哪些部分VirSim有哪几类窗口3-6. Given the data in Table 0.1 for a short channel NMOS transistor withVDSAT = 0.6 V and k=100 A/V 2, calculate VT0, , , 2| f|, and W / L:解答:对于短沟道器件： 2 mini()(1)DGSTDSV
4、WIkLmin,DSATV在选择公式的时候，首先要确定工作区域，表格中的所有V DS均大于V DSAT，所以不可能工作在线性区域。如果工作在饱和区域则：VT 应该满足 : VGS-VT tpHL 因为 RL=75k远大于有效线性电阻 effective linearized on-resistance of M1.5-5 The next figure shows two implementations of MOS inverters. The first inverter uses onlyNMOS transistors. Calculate VOH, VOL, VM for each
5、case. 有的参数参考表1解答：电路 A.VOH: 当 M1关掉， M2 的阈值是:当下面条件满足的时候，M2将关闭:所以 VOUT=VOH=1.765VVOL: 假设 VIN=VDD=2.5V.我们期望 VOUT 为低, 因此我们可以假设 M2 工作在速度饱和区，而 M1 工作在线性区域.因为 ID1= ID2 , 所以 VOUT=VOL=0.263V, 假设成立VM: 当V M=VIN=VOUT.假设两晶体管均工作在速度饱和区域, 我们得到下面两个方程:设 ID1=ID2, 得到 VM=1.269V电路 B.当 VIN=0V, NMOS 关掉，PMOS 打开，并把V OUT拉到VDD,
6、so V OH=2.5. 同样, 当 VIN=2.5V, the PMOS关掉，NMOS 把 VOUT拉到地, 所以 VOL=0V.为了计算 VM ： VM=VIN=VOUT.假设两晶体管均工作在速度饱和区域，可以得到下面两组方程.设 ID3+ ID2 =0 ,可以得到r V M = 1.095V.所以假设两晶体管均工作在速度饱和区域是正确的.5-7 Consider the circuit in Figure 5.5. Device M1 is a standard NMOS device. Device M2 has allthe same properties as M1, except
7、 that its device threshold voltage is negative and has a valueof -0.4V. Assume that all the current equations and inequality equations (to determine themode of operation) for the depletion device M2 are the same as a regular NMOS. Assume thatthe input IN has a 0V to 2.5V swing. ( VDSAT=0.63v)a. Devi
8、ce M2 has its gate terminal connected to its source terminal. If VIN = 0V, what is theoutput voltage? In steady state, what is the mode of operation of device M2 for this input?b. Compute the output voltage for VIN = 2.5V. You may assume that VOUT is small to simplifyyour calculation. In steady stat
9、e, what is the mode of operation of device M2 for thisinput?解答 a当 VIN = 0V ， M1则关掉. M2 开， 因为 VGS=0 VTn2.所以没有电流通过 M2, M2的源漏电压等于0，故M2工作在线性区域，所以VOUT=2.5V.Solution b假设 M1工作在线性区域， M2工作在速度饱和区域，这就意味：因为Vout很小，所以可以忽略V 2out/2,所以可以得到因此我们的假设是合理的。5-15 Sizing a chain of inverters.a. In order to drive a large capa
10、citance (CL = 20 pF) from a minimum size gate (with inputcapacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in Figure， Assume that the propagation delay of a minimum size inverter is 70 ps. Also assumethat the input capacitance of a gate is proportional to its size. Determi
11、ne the sizing of thetwo additional buffer stages that will minimize the propagation delay.b. If you could add any number of stages to achieve the minimum delay, how many stageswould you insert?What is the propagation delay in this case?解答a :当每个buffer的延迟相等的时候，可以得到最小延迟时间.此时每个buffer的尺寸系数分别为 f, f2解答 b:最
12、小延迟时间发生在 f = e的时候，因此6-1 Implement the equation using _()XABCDEFGcomplementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance
13、?解答：因为 _()()ABEF最坏的上拉电阻发生在，只有一个通路存在output node to Vdd.如： ABCDEFG=1111100 and 0101110.最好的上拉电阻发生在： ABCDEFG=0000000.最坏的下拉电阻发生在，只有一个通路存在output node to GND.如： ABCDEFG=0000001 and 0011110.最好的下拉电阻发生在： ABCDEFG=1111111.5章Assume an inverter in the generic 0.25 m CMOS technology designed with a PMOS/NMOS ratio
14、 of 3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W/L =1.5). Please compute VIL, VIH, NML, NMHthe process parameters is presented in table1解：我们首先计算在V M (= 1.25 V)的增益 AVVKLWI outnDSATniDSATMD nn 66 1059)2.061()2/63.0425.1(3.015.)( 5.27. 0.13435.9)( 66 pnDSATSATMDpkVIg gVVM
15、DILgVMIHIHDHVNILNM所以： VIL=1.2V, VIH=1.3V, NML= NMH=1.21.How to deduce that the propagation delay of a gate ? p203 Keep capacitances(CL) small Increase transistor sizes(W/L) Increase VDD (see figure 5.22)减小C L: 增加晶体管的W/L，提高VDD2.Determine the sizes of the inverters in the circuit of Figure 5.22, such
16、that the delay between nodes Out and In is minimized. You may assume that CL = 64 Cg,1P210Figure 5.22,3. For the circuit of Figure 4.11, assume that a driver with a source resistance of is used to drive a 10 cm long, 1 mm wide Al1 wire. And assume that the total k10lumped capacitance for this wire equals 11 pF. When applying a step input(with Vin going from 0
