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1、 毕 业 设 计（论 文）题目：等精度数字频率计的设计Title: Equal Precision Frequency Meter Plan姓 名： 梁 森 专 业： 电子信息工程 学 号： 07061234 指导教师： 陈 坚 东华理工大学毕业设计（论文） ABSTRACTII二 零 一 一 年 六 月东华理工大学毕业设计（论文） 摘要I摘 要频率检测是电子测量领域的最基本也是最重要的测量之一。频率信号抗干扰能力强、易于传输，可以获得较高的测量精度，所以测频率方法的研究越来越受到重视。本课题的等精度数字频率计设计，采用当今电子设计领域流行的EDA 技术，以 CPLD 为核心，配合 AT89C
2、51 单片机，采用多周期同步测频原理，实现了 0.1Hz-50MHz 信号频率的等精度频率测量，此外，该系统还可以测方波信号宽度及高、低电平的占空比。基于传统测频原理的频率计的测量精度将随着被测信号频率的下降而降低，在实用中有很大的局限性，而等精度频率计不但有较高的测量精度，而且在整个测频区域内保持恒定的测试精度。运用等精度测量原理，结合单片机技术设计了一种数字频率计，由于采用了屏蔽驱动电路及数字均值滤波等技术措施，因而能在较宽定的频率范围和幅度范围内对频率，周期，脉宽，占空比等参数进行测量，并可通过调整闸门时间预置测量精度。选取的这种综合测量法作为数字频率计的测量算法，提出了基于 CPLD
3、的数字频率计的设计方案。给出了该设计方案的实际测量效果，证明该设计方案切实可行，能达到较高的频率测量精度。设计中用一块复杂可编程逻辑器件 CPLD(Complex Programmable Logic Device)芯片 EPM7128SLC84-15 完成各种时序逻辑控制、计数功能。在 Quartus II 平台上，用 VHDL 语言编程完成了 CPLD 的软件设计、编译、调试、仿真和下载。用AT89C51 单片机作为系统的主控部件，实现整个电路的测试信号控制、数据运算处理、键盘扫描和控制数码管的显示输出。系统将单片机 AT89C51 的控制灵活性及 CPLD 芯片的现场可编程性相结合，不但
4、大大缩短了开发研制周期，而且使本系统具有结构紧凑、体积小，可靠性高，测频范围宽、精度高等优点。关键词 等精度测量； 单片机； 频率计； 闸门时间东华理工大学毕业设计（论文） ABSTRACTIIABSTRACTIn the field of electronic measurement, the frequency checking is one of mostfundamental and critically important measuring methods. Because frequency signal, whichis easily transported, has stro
5、ng resistance to the disturbance and can be measured withhigh precision, research on the method by measuring frequency have more and moresignificance in the real application.Along with is measured based on the traditional frequency measurement principle frequency meter measuring accuracy the signall
6、ing frequency the drop but to reduce, in is practical has the very big limitation, but and so on the precision frequency meter not only has teaches the high measuring accuracy, moreover maintains the constant test precision in the entire frequency measurement region. Using and so on the precision su
7、rvey principle, unified the monolithic integrated circuit technical design one kind of numeral frequency meter, because has used the shield actuation electric circuit and technical measure and so on digital average value filter, thus could in compared in the frequency range and the scope scope which
8、 the width decided to the frequency, the cycle, the pulse width, occupied parameter and so on spatial ratio carries on the survey, and might through the adjustment strobe time initialization measuring accuracy. Selection this kind of synthesis measured the mensuration took the digital frequency mete
9、r the survey algorithm, proposed based on the CPLD digital frequency meter design proposal. Has produced this design proposal actual survey effect, proved this design proposal is practical and feasible, can achieve the high frequency measurement precision.During the design, a chip EPM7128SLC84_1 S i
10、n CPLD fulfills timing logic control and count function. Under the flat of Quartus II，through VHDL language CPLD software design compilation debug, simulation and download can be carried out. By use of the AT89C51 single chip computer as the main controlling parts, the AT89C51 realizes test signal c
11、ontrol keyboard scan and output display of LED. 东华理工大学毕业设计（论文） ABSTRACTIIIThe system combines the control flexibility of AT89C51 with programmable performance of CPLD，so not only can it shorten the period of the development and research，but also has the advantages of compact structure little volume high reliability wide scope and high precision.Keywords： Precision survey; monolithic integrated circuit; frequency meter, strobe tim东华理工大学毕业设计（论文） 目录1目 录摘 要 .IABSTRACT.II第一章 绪 论 .11.1 背景 .11.2 研究内容及相关技术 .11.3 测量原理 .2第二章 总体设计思路 .32.1 多周期同步测量方法 .32.2 等精度测量原理 .32.3 设计要求 .6第三章 硬件电路设计 .
