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1、1,Digital Logic Design and ApplicationLecture #21,Counter,UESTC, Spring 2013,2,5. Decoding Binary-Counter States,The decoder outputs may contain “glitch” on state transitions where two or more counter bits change. function hazard,3,Decoder Waveforms,The decoder outputs may contain “glitch” on state
2、transitions where two or more counter bits change. function hazard,4,Glitch-free outputs,Registered outputs delayed by one clock tick.,5,6. Cascading Counter (synchronous),计数范围：0 255,99,两个芯片同步工作,6,RCO=QDQCQBQA,RCO-in,1,0,Counting ,Hold ,低片计数器每计满一个周期后，高片计一个数。,7,6. Cascading Counter (asynchronous),思考：
3、利用低位的进位控制高位的时钟行不行？, 两个芯片异步工作。,8,7. Modulo-m Counter,Use SSI devices state machine design using gates and flip-flops Use MSI counter realize a modulo-m counter using an n-bit binary counter Consider two cases m 2n, Using clear or load inputs, Cascading Counter (a)synchronous),9,Design a modulo-11 cou
4、nter using a 74x163, m2n,Clear after Count = (1010)B= (10)D 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,CLR_L asserted,Note : modulo-11 Clear after Count = (10)D,0, 1, 2, 3, 10,10,Quiz：如果是74x161 （异步清零） 可以这样连接吗？,利用1011状态异步清零，会出现“毛刺”,Design a modulo-11 counter using a 74x163, m2n,Clear after Count = (1010)B= (10
5、)D 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, ,0 1 0 1,不可，1010状态将会以“毛刺”形态出现，造成少计一个数的行为。,1 1 0,74X161,11,Design a modulo-11 counter using a 74x163,Load 5 (0101)2 after Count = 15 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, m2n,LD_L asserted, 5, 6, 15,12,Design a modulo-11 counter using a 74x163,Load 01
6、01 (5) after Count = 15 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, , m2n,1 0 1 0,清零法需要额外设计进位输出端，置数法不需要 Quiz: use states 313 to build a modulo-11 counter?,13,Using a 74x163 as a excess-3 counter,Counting from 3 to 12,LD_L asserted,14,1 1 0 0,Using a 74x163 as a excess-3 counter,Counting from 3 to 1
7、2,0 0 1 1,15,Q3 10, duty cycle = 50,16,Modulo-m Counter ( m2n ),Cascade, then clear or load Design a modulo-193 counter using 74x163 Cascade two 163 to obtain a 8-bit counter (0255) Clear after Count = 192 (1100 0000) Load 63 (0011 1111) after Count = 255 25619363 If m = m1m2 Realize m1 and m2 respectively, then cascade,17,6310 = ( 0011 1111 )2,18,19,Example: analysis the following circuit,QD QC QB QA 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1,20,Exercise: analysis the following circuit,模12计数器 QD：12分频 占空比50,
