Copyright 2014-2015 Xilinx . Page 1 XC7A15TXC7A35TXC7A50TXC7A75TXC7A100TXC7A200T 16,64033,28052,16075,520101,440215,360 Slices2,6005,2008,15011,80015,85033,650 20,80041,60065,20094,400126,800269,200 2004006008921,1882,888 255075105135365 9001,8002,7003,7804,86013,140 Clock Resources5556610 250250250300300500 120120120144144240 4590120180240740 111111 111111 111111 4448816 -1, -2-1, -2-1, -2-1, -2-1, -2-1, -2 -2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3 -1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L Package(3), (4)Dimensions (mm) CPG23610 x 10106 (2)106 (2)106 (2) CSG32415 x 15210 (0)210 (0)210 (0)210 (0)210 (0) CSG32515 x 15150 (4)150 (4)150 (4) FTG25617 x 17170 (0)170 (0)170 (0)170 (0)170 (0) SBG484 / SBV48419 x 19285 (4) FGG48423 x 23250 (4)250 (4)250 (4)285 (4)285 (4) FBG484 / FBV48423 x 23285 (4) FGG67627 x 27300 (8)300 (8) FBG676 / FBV67627 x 27400 (8) FFG1156 / FFV115635 x 35500 (16) XMP086 (v4.7) Notes: 2. Represents the maximum number of transceivers available. Note that the majority of devices are available without transceivers. See the Package section of this table for details. Footprint Compatible Speed Grades Commercial Extended Logic Resources Industrial CLB Flip-Flops CPG: 0.5 mm Wire-bond chip-scale; CSG: 0.8 mm Wire-bond chip-scale; FTG: 1.0 mm Wire-bond fine-pitch; SBG / SBV: 0.8 mm Lidless flip-chip; FGG: 1.0 mm Wire-bond fine-pitch; FBG / FBV 1.0 mm Lidless flip-chip; FFG / FFV: 1.0 mm Flip-chip fine-pitch Logic Cells Maximum Distributed RAM (Kb) Block RAM/FIFO w/ ECC (36 Kb each) Total Block RAM (Kb) CMTs (1 MMCM + 1 PLL) 4. Device migration is available within the Artix-7 family for like packages but is not supported between other 7 series families. 3. Leaded package option available for all packages. See DS180, 7 Series FPGAs Overview for details. 1. Supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates. Available User I/O: 3.3V SelectIO HR I/O (GTP Transceivers) Artix-7 FPGAs Footprint Compatible Embedded Hard IP Resources DSP Slices PCIe Gen2(1) Analog Mixed Signal (AMS) / XADC Configuration AES / HMAC Blocks GTP Transceivers (6.6 Gb/s Max Rate)(2) I/O Resources Maximum Single-Ended I/O Maximum Differential I/O Pairs Part Number Memory Resources Artix-7 FPGAs Optimized for Lowest Cost and Lowest Power Applications (1.0V, 0.95V, 0.9V) Copyright 2014-2015 Xilinx . Page 2 XC7K70TXC7K160TXC7K325TXC7K355TXC7K410TXC7K420TXC7K480T XCE7K325TXCE7K355TXCE7K410TXCE7K420TXCE7K480T 10,25025,35050,95055,65063,55065,15074,650 65,600162,240326,080356,160406,720416,960477,760 82,000202,800407,600445,200508,400521,200597,200 8382,1884,0005,0885,6635,9386,788 135325445715795835955 4,86011,70016,02025,74028,62030,06034,380 Clock Resources681061088 300400500300500400400 144192240144240192192 2406008401,4401,5401,6801,920 1111111 1111111 1111111 881624163232 -1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2 -2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3 -1, -2-1, -2, -2L-1, -2, -2L-1, -2, -2L-1, -2, -2L-1, -2, -2L-1, -2, -2L Package(3)Dimensions (mm) FBG484 / FBV48423 x 23185, 100 (4)185, 100 (4) FBG676 / FBV67627 x 27200, 100 (8)250, 150 (8)250, 150 (8)250, 150 (8) FFG676 / FFV67627 x 27250, 150 (8)250, 150 (8)250, 150 (8) FBG900 / FBV90031 x 31350, 150 (16)350, 150 (16) FFG900 / FFV90031 x 31350, 150 (16)350, 150 (16) FFG901 / FFV90131 x 31300, 0 (24)380, 0 (28)380, 0 (28) FFG1156 / FFV115635 x 35400, 0 (32)400, 0 (32) XMP085 (v3.8) FBG / FBV: 1.0 mm Lidless flip-chip; FFG / FFV: 1.0 mm Flip-chip fine-pitch Notes: 1. EasyPath solutions provide a fast and conversion-free path for cost reduction. 3. See DS180, 7 Series FPGAs Overview for package details. Footprint Compatible Footprint Compatible Memory Resources Maximum Distributed RAM (Kb) Block RAM/FIFO w/ ECC (36 Kb each) Total Block RAM (Kb) Commercial Industrial I/O Resources Maximum Single-Ended I/O Maximum Differential I/O Pairs Integrated IP Resources DSP48 Slices PCIe Gen2(2) Analog Mixed Signal (AMS) / XADC Part Number CMTs (1 MMCM + 1 PLL) Available User I/O: 3.3V HR I/O, 1.8V HP I/Os (GTX) 2. Hard block supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates. Gen3 supported with soft IP. Slices EasyPath Cost Reduction Solutions(1) Logic Cells CLB Flip-Flops Configuration AES / HMAC Blocks Logic Resources Speed Grades GTX Transceivers (12.5 Gb/s Max Rate) Extended Kintex-7 FPGAs Kintex-7 FPGAs Optimized for Best Price-Performance (1.0V, 0.95V, 0.9V) Copyright 2014-2015 Xilinx . Page 3 XC7V585TXC7V2000TXC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690TXC7VX980TXC7VX1140TXC7VH580TXC7VH870T XCE7V585TXCE7VX330TXCE7VX415TXCE7VX485TXCE7VX550TXCE7VX690TXCE7VX980T 91,050305,40051,00064,40075,90086,600108,300153,000178,00090,700136,900 582,7201,954,560326,400412,160485,760554,240693,120979,2001,139,200580,480876,160 728,4002,443,200408,000515,200607,200692,800866,4001,224,0001,424,000725,6001,095,200 6,93821,5504,3886,5258,1758,72510,88813,83817,7008,85013,275 7951,2927508801,0301,1801,4701,5001,8。