《时序逻辑电路的设计ppt课件》由会员分享，可在线阅读，更多相关《时序逻辑电路的设计ppt课件（73页珍藏版）》请在金锄头文库上搜索。
1、时序逻辑电路的设计,基本时序电路的设计包括： 触发器、寄存器、计数器、分频器、信号发生器等。,1.时钟信号常用的描述方式： （1）进程的敏感信号有时钟信号，在进程内部用IF语句描述时钟的边沿条件。 （2）在进程中用WAIT UNTIL语句描述时钟信号，此时进程没有相应的敏感信号。,注意： （1）在对时钟边沿说明时，要注明是上升沿还是下降沿。 （1）进程中只能描述一个时钟信号（可综合）。,一时序电路特殊信号的描述,最常用的时钟沿表述： 上升沿：clockEVENT AND clock=1 下降沿：clock EVENT AND clock=0,2. 触发器的复位信号描述 （1）同步复位 （2）异
2、步复位,二常用时序电路设计,1. 触发器（Flip_Flop）,（1）D触发器,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff1 IS PORT(clk,d: IN STD_LOGIC; q: OUT STD_LOGIC); END dff1; PROCESS(clk) BEGIN IF (clkevent AND clk =1) THEN q=d; END IF; END PROCESS; END hav;,（2）异步置位/复位D触发器,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTIT
3、Y dff2 IS PORT(clk,d,clr, pset : IN STD_LOGIC; q: OUT STD_LOGIC); END dff2; ARCHITECTURE hav OF dff2 IS BEGIN PROCESS(clk,pset,clr) BEGIN IF(pset=1) THEN q=1; ELSIF (clr=1) THEN q=0; ELSIF (clkevent AND clk =1) THEN q=d; END IF; END PROCESS; END hav;,（3）同步置位/复位D触发器,LIBRARY IEEE; USE IEEE.STD_LOGIC_1
4、164.ALL; ENTITY dff3 IS PORT(clk,d,clr, pset : IN STD_LOGIC; q: OUT STD_LOGIC); END dff3; ARCHITECTURE hav OF dff3 IS BEGIN PROCESS(clk,pset,clr) BEGIN IF (clkevent AND clk =1) THEN IF(pset=1) THEN q=1; ELSIF (clr=1) THEN q=0; ELSE q=d; END IF; END IF; END PROCESS; END hav;,（4）带有置位复位的锁存器（Latch）,LIBR
5、ARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY latch1 IS PORT(gate,d,clr,pset : IN STD_LOGIC; -gate为电平信号 q: OUT STD_LOGIC); END latch1; ARCHITECTURE hav OF latch1 IS BEGIN PROCESS(gate,d,clr,pset) BEGIN IF (pset=1) THEN q=1; ELSIF (clr=1) THEN q=0; ELSIF(gate=1) THEN q=d; END IF; END PROCESS; END hav
6、;,（5）T触发器,当控制信号T=1时，每来一个时钟信号它的状态就翻转一次； 当T=0时，时钟信号到达后它的状态保持不变。,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tff1 IS PORT(clk,t: IN STD_LOGIC; q: BUFFER STD_LOGIC); END tff1; ARCHITECTURE hav OF tff1 IS BEGIN PROCESS(clk,t) BEGIN IF (clkevent AND clk =1) THEN IF (t=1) THEN q=not q; END IF; END IF
7、; END PROCESS; END hav;,LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY RSFF2 IS PORT ( clk, S, R : IN std_logic; Q, QF : OUT std_logic ); END RSFF2; ARCHITECTURE BHV OF RSFF2 IS BEGIN P1: PROCESS(clk,S,R) VARIABLE D : STD_LOGIC; BEGIN IF (clkevent AND clk =1) THEN IF R = 1 and S = 1 THEN REPORT B
8、OTH R AND S IS 1; -报告出错信息 ELSIF R = 1 and S = 0 THEN D := 0; ELSIF R = 0 and S = 1 THEN D := 1 ; END IF; END IF; Q = D; QF = NOT D; END PROCESS; END BHV;,（6）RS触发器,（7）JK触发器,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY jkff1 IS PORT(clk,j,k: IN STD_LOGIC; q,qn: BUFFER STD_LOGIC); END jkff1; ARCHI
9、TECTURE hav OF jkff1 IS BEGIN PROCESS(clk,j,k) VARIABLE D : std_logic; BEGIN IF (clkevent AND clk =1) THEN IF (j=1 AND k=0) THEN D:=1; ELSIF (j=0 AND k=1) THEN D:=0; ELSIF (j=0 AND k=0) THEN D:= D; ELSE D:= NOT D; END IF; END IF; q = D; qn = NOT D; END PROCESS; END hav;,2. 寄存器,8位串行输入，串行输出移位寄存器（多个触发器
10、连接起来）。,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift8_1 IS PORT (a,clk:IN STD_LOGIC; b: OUT STD_LOGIC); END shift8_1; ARCHITECTURE sample OF shift8_1 IS COMPONENT dff PORT (d,clk :IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; SIGNAL z: STD_LOGIC_VECTOR(0 TO 8); BEGIN z(0)=a; g1: FOR i IN
11、 0 TO 7 GENERATE dffx: dff PORT MAP (z(i),clk,z(i+1); END GENERATE; b=z(8); END sample;,方法（1）结构描述,方法（2） 描述信号的传递过程，信号流的方式,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift8_2 IS PORT (a, clk:IN STD_LOGIC; b: OUT STD_LOGIC); END shift8_2; ARCHITECTURE rt1 OF shift8_2 IS SIGNAL s1,s2,s3,s4,s5,s6,
12、s7: STD_LOGIC; BEGIN PROCESS(clk) BEGIN IF(clkEVENT AND clk=1) THEN s1=a; s2=s1; s3=s2; s4=s3; s5=s4; s6=s5; s7=s6; b=s7; END IF; END PROCESS; END rt1;,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift8_2 IS PORT (a,clk:IN STD_LOGIC; b: OUT STD_LOGIC); END shift8_2; ARCHITECTURE rt1 OF shift8_
13、2 IS SIGNAL s: STD_LOGIC_VECTOR(0 TO 8); BEGIN PROCESS(clk) BEGIN IF(clkEVENT AND clk=1) THEN FOR i IN 0 TO 7 LOOP s(i+1)=s(i); END LOOP; END IF; END PROCESS; s(0)=a; b=s(8); END rt1;,采用循环语句：,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift IS PORT (clk,load:IN STD_LOGIC; din: IN STD_LOGIC_VE
14、CTOR(7 DOWNTO 0); dout: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); qb: OUT STD_LOGIC); END shift; ARCHITECTURE behav OF shift IS SIGNAL reg8: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(clk,load) BEGIN IF clkEVENT AND clk=1 THEN IF load=1 THEN reg8=din; ELSE reg8(6 DOWNTO 0)=reg8(7 DOWNTO 1); END IF; END IF;
15、 END PROCESS; qb=reg8(0); dout=reg8; END behav;,例5-8 含预置、并行输出的8位移位寄存器 P151,例5-9 移位模式可控的8位移位寄存器 P152 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SHIFT IS PORT (CLK,C0 : IN STD_LOGIC; -时钟和进位输入 MD : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -移位模式控制字 D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -待加载移位的数据 QB : OUT
16、STD_LOGIC_VECTOR(7 DOWNTO 0); -移位数据输出 CN : OUT STD_LOGIC); -进位输出 END ENTITY; ARCHITECTURE BEHAV OF SHIFT IS SIGNAL REG : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CY : STD_LOGIC ; BEGIN,PROCESS (CLK,MD,C0) BEGIN IF CLKEVENT AND CLK = 1 THEN CASE MD IS WHEN 001 = REG(0) REG(0) REG(7) REG(7) REG(7 DOWNTO 0) REG = REG ; CY = CY ; -保持 END
