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1、Introduce the PCB Layout,Presented by Nina Miao NDC 2004-02 Ver.2.0,1,PCB Layout System,1. Padstack 2. Component Symbols 3. Board Design 4. Importing Logic Information into Allegro 5. Setting Design Constraints 6. Component Placement 7. Routing 8. Via 9. Test Point,2,1. Padstack,1.1 Create a flash s
2、ymbol 1.2 Create padstacks 1.3 Anatomy of a Padstack 1.4 Padstack Details,3,1. Padstack(Cont.),1.1 Create a flash symbol used for thermal reliefs. A thermal relief is a special pattern used where connections are made to an embedded plane that allows heat to concentrate near a pin or via during the s
3、oldering process.,4,1. Padstack(Cont.),1.2 Create padstacks for a number of typical pins and device types: a. Create a padstack for a through-hole pin. b. Create a padstack for pin 1 of a through-hole pin. c. Create a padstack for a surface-mounted device.,5,1. Padstack(Cont.),1.3 Anatomy of a Padst
4、ack,6,1. Padstack(Cont.),1.4 Padstack Details,7,2. Package symbol,2.1 Symbol types,8,2. Package symbol(Cont.),2.2.1 Footprint symbols model the components that are placed on the printed circuit board. 2.2.2 styles of footprints including DIP, SOIC,PLCC, QFP and so on . 2.2.3 When create the footprin
5、t,we will define information such as design units, number of pins, pin spacing, padstacks to use,and so forth.,9,2. Package symbol(Cont.),2.2.4 Package outline.,10,3. Board Design,3. 1 Board Outline,11,3. Board Design(Cont.),12,3. Board Design(Cont.),3.2 Board is composed of:,13,3. Board Design(Cont
6、.),3.3 Board Stack-Up,14,3. Board Design(Cont.),4.3 mils Prepreg, 48 mils Core：FR4,4.5 mils Prepreg,1.FR4 is a special material of Core.,2.Board impedance6010。,15,3. Board Design(Cont.),3.4 Power divide,16,4. Importing Logic Information into Allegro,4.1 Layout Process 4.2 Bring the schematic data 4.
7、3 Import logic information 4.3.1 Concept Logic Import 4.3.2 Capture Logic import 4.3.3 Third-Party Logic Import,17,4. Importing Logic Information into Allegro(Cont.),4.1 Layout Process,18,4. Importing Logic Information into Allegro(Cont.),4.2 Bring schematic data from the Concept tool, Capture tool,
8、 or a third-party front-end tool. 4.3 Set up and import logic information into Allegro from one of the these three schematic environments: Concept-HDL Capture Third-party,19,4. Importing Logic Information into Allegro(Cont.),4.3.1 Concept Logic Import,20,4. Importing Logic Information into Allegro(C
9、ont.),4.3.2 Capture Logic import,21,4. Importing Logic Information into Allegro(Cont.),4.3.3 Third-Party Logic Import,22,4. Importing Logic Information into Allegro(Cont.),23,5.Setting Design Constraints,24,5.Setting Design Constraints(Cont.),5.1 There are four types of design rules: 5.1.1 Spacing R
10、ule Set: Clearances between lines, pads, vias, and copper areas (shapes) 5.1.2 Physical Rule Set: Line width and layer restrictions 5.1.3 Design Constraints: Package checks, solder mask checks and negative plane island checks,25,5.Setting Design Constraints(Cont.),5.1.4 Electrical Constraint Sets: P
11、erformance characteristics (crosstalk and propagation delay).,26,5.Setting Design Constraints(Cont.),5.2 There are two levels of detail for design rules: 5.2.1 Standard rules: Describe the majority of nets in a design. These global rules are applied to all nets (all nets are created equal). 5.2.2 Ex
12、tended rules: Are performance related, and are assigned on a net-by-net basis. Timing and speed considerations (net length and propagation delay) Noise and distortion concerns (crosstalk, reflection, impedence).,27,6. Component Placement,6.1 The prerequisites for manual placement are: 6.1.1Symbols:
13、The package symbols and padstacks required for parts in the netlist must exist. 6.1.2Netlist: You must load a schematic database into an Allegro design file(.brd). 6.1.3Floorplanning: You can create a “block diagram” of the logical functions that need to be arranged on the board by using Rooms.,28,6
14、.Component Placement(Cont.),6.2 Component placement strategy Create rooms for floorplanning. Assign reference designators to preplaced devices. Place I/O bound devices. Place critical logic functions. Evaluate and revise placement. Place bulk decoupling and bypass caps. Use reports to aid placement
15、process.,29,6.Component Placement(Cont.),6.3 Set drawing parameters. Place the mechanical symbol. Add format symbols. Add package symbols. Set color and visibility. Define the cross section (layer stackup).,30,7. Routing,7.1 Interactive routing modes Define net properties before adding etch. Common
16、net properties used with interactive route are: MIN_LINE_WIDTH MIN_NECK_WIDTH NO_RAT FIXED Adding signal connections Deleting signal connections Inserting vias. 7.2Automatic Routing modes,31,8.1 Type of Via: through via blind via buried via,32,9. Test Point,9.1 Bareboard a. Electrical continuity check (opens and shorts) b. Performed
