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1、 摘要一种低功耗全MOS基准电压源的设计摘 要随着电子产品的更新和互联网的发展，集成电路的功耗逐渐成为制约电子产品小型化和长续航的瓶颈问题。为了适应集成电路低功耗的趋势，越来越多基准电压源的研究和设计进入了纳瓦水平。但是，传统的基准电压源电路中，电阻往往是不可缺少的，低成本的要求使得集成电路的数字化程度逐渐加深，因此研究设计结构简单，占用面积小，可使用标准数字 CMOS 技术实现的低功耗基准电压源具有重要的意义。本文设计的低功耗基准电压源基于MOSFET亚阈值区的特性，MOSFET阈值电压作为重点分析和考虑的因素。从物理结构分析了亚阈值区MOSFET的原理及特点，讨论了影响MOS管阈值电压大小
2、的因素，分析了亚阈值管的部分电流电压特性。文中详细的对基准电压源整体电路结构及其工作原理作了简单介绍，并给出了各个主要子模块电路的设计。本设计基于SMIC 0.18um CMOS工艺，首先设计了一种全MOSFET结构的低功耗基准电压源，性能基本达到指标要求，利用Cadence Spectre完成电路仿真并完成版图设计。本文设计的低功耗基准电压源的优势以及创新之处在于：实现了低的电路功耗，在1.8V电源电压下，输出电压为470mV时，电路的总功耗约为111nW，电源抑制比达到-30db以上，温度系数为92.8ppm/，最终设计达到了预期的设计目标。版图设计部分对每一个模块都进行了优化，整体采用三
3、层金属线连接，减少了对工艺的需求。利用Calibre软件完成了电路DRC验证与LVS验证，最终完成可流片的版图，总面积为210um*140um，实现了无电阻，无双极型晶体管的全MOS结构，占用面积小，与数字CMOS工艺兼容，节省生产制造成本。关键词：低功耗，全MOS结构，基准电压源39Design of Low Power Consumption All MOS Reference Voltage SourceAbstractWith the updating of electronic products and the progress of the Internet, the power
4、consumption of integrated circuits has gradually become a bottleneck restricting the miniaturization and long-term sustainability of electronic products. In order to adapt to the trend of ultra-low power consumption of integrated circuits, more and more research and design of reference voltage sourc
5、es have entered the Nava level. However, in the traditional voltage reference circuit, resistance is often indispensable. The requirement of low cost makes the digitization of integrated circuits deepen gradually. Therefore, the research and design of ultra-low power reference voltage source with si
6、mple structure and small occupancy area can be realized by using standard digital CMOS technology.The ultra-low power reference voltage source designed in this paper is based on the characteristics of the sub-threshold region of MOSFET. The threshold voltage of MOSFET is the key factor for analysis
7、and consideration. The principle and characteristics of the sub-threshold MOSFET are analyzed from the physical structure. The factors affecting the threshold voltage of the MOSFET are discussed. The partial current and voltage characteristics of the sub-threshold MOSFET are analyzed. In this paper,
8、 the overall circuit structure and working principle of the reference voltage source are introduced in detail, and the design of each main sub-module circuit is given.Based on SMIC 0.18um CMOS technology, an ultra-low power reference voltage source with all-MOSFET structure is designed. Its performa
9、nce basically meets the requirements. The circuit simulation and layout design are completed by Cadence Spectre. The advantages and innovations of the ultra-low power reference voltage source designed in this paper lie in the realization of ultra-low circuit power consumption. When the output voltag
10、e is 470mV at 1.8V supply voltage, the total power consumption of the circuit is about 111nW, the power supply rejection ratio is above - 30db, and the temperature coefficient is 92.8ppm/. Finally, the design achieves the expected design goal. In the layout design part, each module is optimized, and
11、 only two layers of metal wires are used to connect the whole module, which reduces the demand for process. The DRC verification and LVS verification of the circuit are completed by Calibre software. Finally, the layout of the flow sheet is completed. The total area is 210 um*140 um. The all-MOS str
12、ucture without resistor and bipolar transistor is realized. The occupied area is small. It is compatible with the digital CMOS process and saves the cost of production and manufacture.Key words:ultra-low consumption, All-MOS,Voltage reference目录摘 要IABSTRACTII第1章绪 论61.1 背景与意义61.2 研究历史及现状61.3 研究内容与方法7第
13、2章关键技术介绍82.1 全MOSFET结构82.2 电压模基准82.3 拓扑结构92.4 全定制设计102.5 CMOS基准源主要性能指标102.5.1 温度系数（Temperature Coefficient，TC）102.5.2 电源抑制比（Power Supply Rejection Ratio，PSRR）102.5.3 功耗（Power Consumption）10第3章电路模块设计123.1 一种结构新颖的纳安电流偏置电路设计123.2 CTAT电压产生电路设计143.3 PTAT电压补偿电路设计153.4 整体结构及基准输出17第4章电路仿真184.1 整体电路功能仿真184.2
14、 直流特性仿真194.3 基准输出电压的温度特性194.4 电源抑制比仿真204.5 基准源部分性能20第5章基准电压源的版图设计225.1 集成电路版图设计（LAYOUT）概述225.2 MOS管的匹配225.3 NMOS/PMOS晶体管的版图实现235.4 串联晶体管的版图实现245.5 并联晶体管的版图实现245.6 p18与p33的版图对比265.6低功耗全MOS基准电压源版图设计26第6章基准电压源的版图验证296.1 验证概述296.2 版图验证的项目296.2.1 设计规则检查（DRC）296.2.2 版图和电路图一致性比较（LVS）306.3基准电压源的设计规则检查（DRC）3
15、16.4基准电压源的版图电路图对比检查（LVS）32第7章结 论34参考文献35致 谢36第1章绪 论近几年来，集成电路在当前电子科技领域不断发展，所具备的信息处理能力和运算速度随着技术的发展越来越高，然而随着运算速度和强度的增加，功耗也越来越大，而在集成电路设备的设计过程中，集成电路的设计及运用者只能从集成电路的性能和功耗中进行二选一或者折中选择，对于当前集成电路在纳米领域的发展产生了严重的制约，也影响了集成电路的超大规模集成发展。由于集成电路功耗降低方面的技术难题，阻碍了集成电路的继续发展，因此对该技术难题的破解是当前学术界共同研究和探讨的问题。本章首先介绍了低功耗CMOS基准电压源的背景与意义；然后重点介绍低功耗CMOS基准电压源研究历史及现状和研究内容与方法。1.1 背景与意义随着CMOS半导体工艺制造技术的提高，面积和速度已不再是现在半导体集成电路设计中需要考虑的唯一目标，耗逐渐成为制约集成电路发展的重要问题。尤其随着物联网和可穿戴电子产品市场的发展，低功耗集成电路设计面临严峻的考验。为了适应集成电路低功耗的趋势，越来越多基准电压源的研究和设计进入了纳瓦水平；在传统的基准电压源电路中，电阻常常是决定其性能的关键，并且电路中通过的电流值越小则所需电阻值越大，相应的占用面积
