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1、Steven Shi steven shi Telecom AFA Team Texas Instruments High Speed Layout Considerations 1 General Considerations a Models Resistors Capacitors Inductors and Circuit Board 2 High Speed Op Amp Layout a Input and output considerations b Signal routing c Bypass capacitors d Layout examples 3 High Spee
2、d ADC DAC Design and Layout a Input and output considerations b Bypass Capacitors c Splitting the Ground Plane 4 High Speed Clock Layout Guidelines a Coupling Interference or Cross Talk b Power Supply Filtering c Power Supply Bypassing especially clocks Remember Current Return Path tw h lnL nH 0 8 5
3、 98 2x 0 8 5 98 1 410 264x tw h ln r C pF h t w r Component Microstrip Copper Traces Purpose Interconnect two or more points Problem Inductance and Capacitance x length of trace cm w width of trace cm h thickness of board cm t thickness of trace cm er PCB dielectric constant FR 4 4 5 0 8mm 0 031 tra
4、ce on 0 8mm 0 031 thick PCB FR 4 has 4nH and 0 8pF per cm 10nH and 2 0pF per inch L nH C pF ps cm Tp31 6 C pF L nH Z031 6 PCB Components 0 0886 h C pF A r Component Copper Planes Purpose Used For Ground Planes and Power Planes Problem Stray Capacitance on Signal Traces Benefit At high frequencies 1G
5、 Adds Bypass Capacitance with low Inductance h separation between planes cm A area of common planes l w cm2 er PCB dielectric constant FR 4 4 5 0 8mm 0 031 thick PCB FR 4 has 0 5pF per cm2 32 7pF per inch2 h r w lA PCB Components 0 4mm 0 0157 via with 1 6mm 0 063 thick PCB has 1 2nH 1 6mm 0 063 Clea
6、rance hole around 0 8mm 0 031 pad on FR 4 has 0 4pF Component Vias Purpose Interconnect traces on different layers Problem Inductance and Capacitance d h ln h L nH 4 1 5 12 1 05550 dd d h C pF r er PCB dielectric constant FR 4 4 5 L nH C pF ps cm Tp31 6 C pF L nH Z031 6 PCB Components 1 General Cons
7、iderations a Models Resistors Capacitors Inductors and Circuit Board 2 High Speed Op Amp Layout a Input and output considerations b Signal routing c Bypass capacitors d Layout examples 3 High Speed ADC DAC Design and Layout a Input and output considerations b Bypass Capacitors c Splitting the Ground
8、 Plane 4 High Speed Clock Layout Guidelines a Coupling Interference or Cross Talk b Power Supply Filtering c Power Supply Bypassing 100H 98 3 Outer Ground Layers should be Via Stitched to create the PCB faraday cage at a spacing equal to 4 of the highest harmonics on the board 1 1 2 2 3 3 E Filed Cancellation E FieldE FieldE FieldE Field Same Capacitance Value Opposite Direction Decoupling Capacitors Place Decoupling Capacitors in opposite directions to achieve filed cancellation The End Thank You Are There Any Questions
