《8位ALU(算术逻辑单元)verilog语言.doc》由会员分享，可在线阅读，更多相关《8位ALU(算术逻辑单元)verilog语言.doc（10页珍藏版）》请在金锄头文库上搜索。
1、 大连理工大学城市学院 FPGA实验报告 实验内容：8位ALU系别班级：电子1004班学号：姓名：日期：2013.4.14 一设计概述： 一种基于可编程逻辑器件FPGA和硬件描述语言的8位的ALU的设计方法。该ALU采用层次设计方法，有寄存器模块、控制模块和显示模块组成，能实现8位无符号数的取值、加减和4种逻辑运算（与、或、异或、同或）。该ALU在QuartusII软件环境下进行功能仿真，通过DE2验证。二 设计功能：1、该处理器的数据宽度为8bit，可以实现算术加法、减法、逻辑与、逻辑或、逻辑非、逻辑与非、逻辑或非和逻辑异或等8种运算。2、用选择端opcode 2:0 选择8种运算，2个操作
2、数分别是a_r 7:0和b_r7:0，运算结果是alu_out7:0；并定义选择如下。选择端opcode2:0运算结果解释说明000A操作数a_r7:0001B操作数b_r7:0010算术加法011算术减法100逻辑与101逻辑或110逻辑异或111逻辑同或3、使用DE2板上的3个拨码开关设置当前ALU的运算功能，再由8个拨码开关给定数据A和数据B，由一个按键key手动提供脉冲。三 设计方案：本设计共有5个模块。1）脉冲输出器（key手动脉冲），计数依次产生4个脉冲到各个部件，第一个脉冲启动信号。2）寄存器A，第二个脉冲来时锁存数据A，并在数码管上显示。3）寄存器B，第三个脉冲来时锁存数据B，
3、并在数码管上显示。4）8位ALU，第四个脉冲来时进行运算，并锁存结果alu_out。5）结果显示器，将结果显示通过DE2上的数码管显示。四 程序分析：主程序模块:module alu8(clk,clk_r,rst,a,b,alu_out,opcode,sw_ab,HEX1, HEX0, HEX7, HEX6, HEX5, HEX4);input clk,rst,clk_r;input 7:0 sw_ab;input 2:0 opcode;output 6:0 HEX1, HEX0, HEX7, HEX6, HEX5, HEX4;output 7:0 a;output 7:0 b;output
4、7:0 alu_out;rega U1(.clk(clk),.rst(rst),.sw_ab(sw_ab),.a_r(a),.clk_r(clk_r),.HEX7(HEX7),. HEX6(HEX6);regb U2(.clk(clk),.rst(rst),.sw_ab(sw_ab),.b_r(b),.clk_r(clk_r),.HEX5(HEX5),. HEX4(HEX4);alur U3(.clk(clk),.rst(rst),.a_r(a),.b_r(b),.alu_out(alu_out),.opcode(opcode);digital U4(.clk_r(clk_r),.rst(rs
5、t),.alu_out(alu_out),.HEX1(HEX1),. HEX0(HEX0);endmodule第一位数A模块：module rega (clk,clk_r,rst,sw_ab,a_r,HEX7,HEX6);input 7:0 sw_ab;input clk,clk_r,rst;output 7:0 a_r;reg 7:0 a_r;output reg6:0 HEX7,HEX6;reg 3:0 cnt;always (posedge clk or negedge rst)if(!rst) cnt=1d0;else if(cnt=5) cnt=1d0;else cnt=cnt+1d
6、1;always (posedge clk or negedge rst)if(!rst) a_r=0;else if(cnt=1) a_r=sw_ab;else a_r=a_r;parameter seg0=7b1000000,seg1=7b1111001,seg2=7b0100100,seg3=7b0110000,seg4=7b0011001,seg5=7b0010010,seg6=7b0000010,seg7=7b1111000,seg8=7b0000000,seg9=7b0010000,sega=7b0001000,segb=7b0000011,segc=7b1000110,segd=
7、7b0100001,sege=7b0000110,segf=7b0001110;always (posedge clk_r)case(a_r3:0)4h0: HEX66:0=seg0;4h1: HEX66:0=seg1;4h2: HEX66:0=seg2;4h3: HEX66:0=seg3;4h4: HEX66:0=seg4;4h5: HEX66:0=seg5;4h6: HEX66:0=seg6;4h7: HEX66:0=seg7;4h8: HEX66:0=seg8;4h9: HEX66:0=seg9;4ha: HEX66:0=sega;4hb: HEX66:0=segb;4hc: HEX66
8、:0=segc;4hd: HEX66:0=segd;4he: HEX66:0=sege;4hf: HEX66:0=segf;default:HEX66:0=seg0;endcasealways (posedge clk_r)case(a_r7:4)4h0: HEX76:0=seg0;4h1: HEX76:0=seg1;4h2: HEX76:0=seg2;4h3: HEX76:0=seg3;4h4: HEX76:0=seg4;4h5: HEX76:0=seg5;4h6: HEX76:0=seg6;4h7: HEX76:0=seg7;4h8: HEX76:0=seg8;4h9: HEX76:0=s
9、eg9;4ha: HEX76:0=sega;4hb: HEX76:0=segb;4hc: HEX76:0=segc;4hd: HEX76:0=segd;4he: HEX76:0=sege;4hf: HEX76:0=segf;default:HEX76:0=seg0;endcaseendmodule第二位数B模块：module regb (clk,clk_r,rst,sw_ab,b_r,HEX5,HEX4);input 7:0 sw_ab;input clk,clk_r,rst;output 7:0 b_r;reg 7:0 b_r;output reg6:0 HEX5,HEX4;reg 3:0
10、cnt;always (posedge clk or negedge rst)if(!rst) cnt=1d0;else if(cnt=5) cnt=1d0;else cnt=cnt+1d1;always (posedge clk or negedge rst)if(!rst) b_r=0;else if(cnt=2) b_r=sw_ab;else b_r=b_r;parameter seg0=7b1000000,seg1=7b1111001, seg2=7b0100100,seg3=7b0110000,seg4=7b0011001,seg5=7b0010010,seg6=7b0000010,
11、seg7=7b1111000,seg8=7b0000000,seg9=7b0010000,sega=7b0001000,segb=7b0000011,segc=7b1000110,segd=7b0100001,sege=7b0000110,segf=7b0001110;always (posedge clk_r)case(b_r3:0)4h0: HEX46:0=seg0;4h1: HEX46:0=seg1;4h2: HEX46:0=seg2;4h3: HEX46:0=seg3;4h4: HEX46:0=seg4;4h5: HEX46:0=seg5;4h6: HEX46:0=seg6;4h7:
12、HEX46:0=seg7;4h8: HEX46:0=seg8;4h9: HEX46:0=seg9;4ha: HEX46:0=sega;4hb: HEX46:0=segb;4hc: HEX46:0=segc;4hd: HEX46:0=segd;4he: HEX46:0=sege;4hf: HEX46:0=segf;default:HEX46:0=seg0;endcasealways (posedge clk_r)case(b_r7:4)4h0: HEX56:0=seg0;4h1: HEX56:0=seg1;4h2: HEX56:0=seg2;4h3: HEX56:0=seg3;4h4: HEX5
13、6:0=seg4;4h5: HEX56:0=seg5;4h6: HEX56:0=seg6;4h7: HEX56:0=seg7;4h8: HEX56:0=seg8;4h9: HEX56:0=seg9;4ha: HEX56:0=sega;4hb: HEX56:0=segb;4hc: HEX56:0=segc;4hd: HEX56:0=segd;4he: HEX56:0=sege;4hf: HEX56:0=segf;default:HEX56:0=seg0;endcaseendmodule运算模块：module alur(clk,rst,alu_out,a_r,b_r,opcode,zero);output 7:0 alu_out;output zero;input 7:0 a_r,b_r;input 2:0 opcode;input clk,rst;reg 7:0 alu_out;reg 3:0 cnt;parameter quA=3b000,quB=3b001,ADD=3b010,DEC=3b011,ANDD=3b100,XORR=3b101,XOR=3b110,NXOP=3b111;assign zero=!a_r;always (posedge clk or negedge rst)if(!rst) cnt=1d0;
