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1、 xxx 1 CONTENT 鲽 2 3 3 TONETABA VHD NOTETABS VHDSPEAKER VHD SPEAKERA TONETABASPEAKERA SPEAKER伴 NOTETABS8 138 4Hz 0 25 1 4 NoteTabsROM music ROM ROM VHDL QuartusII 沨 CLK12MHzclock9 12MHz clock9 12MHz CLK8Hzclock2 4Hz SPKOUTSpeaker CODE11 HIGH1 D1 SOF 5 01mif 02LPM ROM 03 04 05 06 07 08 鲽 6 01mif mif
2、4bits 256 7 02LPM ROM 1 block1 bdf LPM ROM 2 cyclone VHDL music vhd 3 4bits 256 4 Mif liangzhu mif finish 8 03 VHDL NoteTabs Speakera ToneTaba NoteTabs vhd Speakera vhd ToneTaba vhd 9 03 LIBRARYIEEE USEIEEE STD LOGIC 1164 ALL USEIEEE STD LOGIC UNSIGNED ALL ENTITYNoteTabsISPORT clk INSTD LOGIC ToneIn
3、dex OUTSTD LOGIC VECTOR 3DOWNTO0 END ARCHITECTUREoneOFNoteTabsISCOMPONENTMUSIC ROMPORT address INSTD LOGIC VECTOR 7DOWNTO0 clock INSTD LOGIC q OUTSTD LOGIC VECTOR 3DOWNTO0 ENDCOMPONENT NoteTabs vhd SIGNALCounter STD LOGIC VECTOR 7DOWNTO0 BEGINCNT8 PROCESS clk Counter BEGINIFCounter 138THENCounterCou
4、nter q ToneIndex clock clk END 10 03 LIBRARYIEEE USEIEEE STD LOGIC 1164 ALL USEIEEE STD LOGIC UNSIGNED ALL ENTITYSpeakeraISPORT clk INSTD LOGIC Tone INSTD LOGIC VECTOR 10DOWNTO0 SpkS OUTSTD LOGIC END ARCHITECTUREoneOFSpeakeraISSIGNALPreCLK FullSpkS STD LOGIC BEGINDivideCLK PROCESS clk VARIABLECount4
5、 STD LOGIC VECTOR 3DOWNTO0 BEGINPreCLK11THENPreCLK 1 Count4 0000 ELSIFclk EVENTANDclk 1 THENCount4 Count4 1 Speakera vhd ENDIF ENDPROCESS GenSpkS PROCESS PreCLK Tone 11VARIABLECount11 STD LOGIC VECTOR 10DOWNTO0 BEGINIFPreCLK EVENTANDPreCLK 1 THENIFCount11 16 7FF THENCount11 Tone FullSpkS 1 ELSECount
6、11 Count11 1 FullSpkS 0 ENDIF ENDIF ENDPROCESS DelaySpkS PROCESS FullSpkS 2 VARIABLECount2 STD LOGIC BEGINIFFullSpkS EVENTANDFullSpkS 1 THENCount2 NOTCount2 IFCount2 1 THENSpkS 1 ELSESpkS 0 ENDIF ENDIF ENDPROCESS END 11 03 LIBRARYIEEE USEIEEE STD LOGIC 1164 ALL ENTITYToneTabaISPORT Index INSTD LOGIC
7、 VECTOR 3DOWNTO0 CODE OUTSTD LOGIC VECTOR 3DOWNTO0 HIGH OUTSTD LOGIC Tone OUTSTD LOGIC VECTOR 10DOWNTO0 END ARCHITECTUREoneOFToneTabaISBEGINSearch PROCESS Index BEGINCASEIndexIS ToneTaba vhd WHEN 0000 ToneToneToneToneToneToneToneToneToneToneToneToneToneNULL ENDCASE ENDPROCESS END 12 04 VHDL Songer v
8、hd 13 04 LIBRARYIEEE USEIEEE STD LOGIC 1164 ALL ENTITYSongerISPORT CLK12MHZ INSTD LOGIC CLK8HZ INSTD LOGIC CODE1 OUTSTD LOGIC VECTOR 3DOWNTO0 HIGH1 OUTSTD LOGIC 8SPKOUT OUTSTD LOGIC END ARCHITECTUREoneOFSongerISCOMPONENTNoteTabsPORT clk INSTD LOGIC ToneIndex OUTSTD LOGIC VECTOR 3DOWNTO0 ENDCOMPONENT
9、 COMPONENTToneTaba Songer vhd PORT Index INSTD LOGIC VECTOR 3DOWNTO0 CODE OUTSTD LOGIC VECTOR 3DOWNTO0 HIGH OUTSTD LOGIC Tone OUTSTD LOGIC VECTOR 10DOWNTO0 ENDCOMPONENT COMPONENTSpeakeraPORT clk INSTD LOGIC Tone INSTD LOGIC VECTOR 10DOWNTO0 SpkS OUTSTD LOGIC ENDCOMPONENT SIGNALTone STD LOGIC VECTOR 10DOWNTO0 SIGNALToneIndex STD LOGIC VECTOR 3DOWNTO0 BEGINu1 NoteTabsPORTMAP clk CLK8HZ ToneIndex ToneIndex u2 ToneTabaPORTMAP Index ToneIndex Tone Tone CODE CODE1 HIGH HIGH1 u3 SpeakeraPORTMAP clk CLK12MHZ Tone Tone SpkS SPKOUT END 14 05 15 06 16 06 17 07 18 THANKS XXX 19
