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1、台大電機系 陳信樹副教授 National Taiwan University Department of Electrical Engineering 設計於深次微米CMOS製程之功率感知高速類比數位轉換積體電路 (Power-Aware High-Speed ADC in Deep Submicron CMOS) 文化大學電機系2011年先進電機電子科技研討會 NTUEE ; Mixed-Signal IC Lab 陳信樹 Outline l Motivation l High-speed ADC IC design example l Digitally-assisted algorit
2、hm and architecture l Circuit implementation l Experimental results l Summary 2 NTUEE ; Mixed-Signal IC Lab 陳信樹 High-Speed ADC Applications lRef 1 3 NTUEE ; Mixed-Signal IC Lab 陳信樹 Power-Aware High-Speed ADC Trends lPower / Energy pHigher resolution requires more energy to achieve. lSpeed / Bandwidt
3、h pResolution and speed are trade-offs. lBottleneck pSAR architecture saves power and chip area, but speed is limited by its conversion algorithm. pPipelined architecture achieves high speed by concurrent operations, but OPAs consume considerable power. lDigitally assisted ADCs pDigitally assisted a
4、lgorithm alleviates analog circuit requirement; therefore, it takes advantages of advanced processes to trade little digital power to gain the benefits from analog part. 4 NTUEE ; Mixed-Signal IC Lab 陳信樹 High-Speed ADC Energy vs. SNDR lEnergy is proportional to resolution (SNDR). lFOM (Power / (Samp
5、le rate * 2ENOB) is an indicator to compare different ADC designs. lState-of-the-art ADC designs approach 10fJ/c.s. Current world record is 4fJ/c.s. l Ref 2 5 NTUEE ; Mixed-Signal IC Lab 陳信樹 High-Speed ADC Bandwidth vs. SNDR lBandwidth is inverse proportional to resolution (SNDR). lState-of-the-art
6、high-speed high-resolution ADCs are limited by clock jitter around 0.1psrms. l Ref 2 6 NTUEE ; Mixed-Signal IC Lab 陳信樹 Experiment 1 - Low-Power High-Speed Two-Step ADC lRearrange the timing of two-channel MDACs and apply a self-timing technique to alleviate comparator comparison time and charge inje
7、ction disturbance lSlightly increases CADC accuracy to ease OPA signal swing design l Ref 3 Technology0.13m Resolution6-bit Active area0.16mm2 Supply voltage1.2V Sample rate1-GS/s SFDR (FinNq)40.7dB SNR (FinNq)33.8dB SNDR (FinNq)33.7dB Power49mW FoM1.24pJ/c.s. 7 NTUEE ; Mixed-Signal IC Lab 陳信樹 lReli
8、eve MSB accuracy requirement by the sub-range concept with overlapping lReduce total input capacitance by using the double-unit- sized coupling-capacitor l Ref 4 Experiment 2 - Low-Power High-Speed Sub-range SAR ADC Technology0.13m Resolution12-bit Active area0.096mm2 Supply voltage1.2V Sample rate1
9、0MS/s SFDR (FinNq)69.8dB SNR (FinNq)61.2dB SNDR (FinNq)59.7dB Power3mW FoM0.38pJ/c.s. 8 NTUEE ; Mixed-Signal IC Lab 陳信樹 lAttain high conversion speed by adopting non-constant-radix switching method lCompared to conventional non-binary designs, its DAC implementation is simpler. Experiment 3 - Low-Po
10、wer High-Speed SAR ADC Technology90nm Resolution10-bit Chip area1.029mm2 Supply voltage1.0V Sample rate40MS/s SFDR (FinNq)61.9dB SNDR (FinNq)54.1dB Power1.34mW FoM81.1fJ/c.s. 9 NTUEE ; Mixed-Signal IC Lab 陳信樹 lAchieve high speed with a low-gain OPA by using digitally- assisted architecture, thus the
11、 OPAs have excellent power efficiency lA simple gain-error self calibration method without external precise references requires only 168 calibration clock cycles. lRef 5 Experiment 4 - Low-Power High-Speed Pipelined ADC Technology90nm Resolution10-bit Active area0.21mm2 Supply voltage1.2V Sample rat
12、e320MS/s SFDR (FinNq)66.7dB SNDR (FinNq)51.2dB Power42mW FoM0.44pJ/c.s. 10 NTUEE ; Mixed-Signal IC Lab 陳信樹 Digitally-Assisted High-Speed ADC Example (Experiment 4) lDigitally assisted architecture is future trend to achieve excellent power efficiency. l10b, several hundreds MS/s Pipeline ADCs are wi
13、dely used in wireless and cloud computing systems but suffer from OPA design in deep submicron CMOS processes. pDecreased OPA DC gain pSmaller signal swing 11 NTUEE ; Mixed-Signal IC Lab 陳信樹 Pipeline ADC Accuracy lOPA gain pLess Ro of MOSFET in advanced technologies pReduced gain from each stage of
14、OPA pMore gain stages introduce poles and decrease bandwidth. pFor 10b accuracy, the 1st stage MDAC requires 66dB OPA DC gain. lCapacitor mismatch pRaw matching can attain 10b accuracy, not an issue! 12 NTUEE ; Mixed-Signal IC Lab 陳信樹 Closed-Loop Gain Error 13 l For finite A, closed-loop gain ACL is
15、 smaller than ideal gain, 1/b. l Gain error can be compensated by adjusting b. NTUEE ; Mixed-Signal IC Lab 陳信樹 l Due to finite A, closed-loop gain is less than ideal value of 4. l b adjustment is proposed to correct MDAC gain error. 14 MDAC Gain Error NTUEE ; Mixed-Signal IC Lab 陳信樹 Proposed MDAC wi
16、th a Calibration Capacitor l A calibration capacitor, Ccal, is added as a positive feedback to adjust b. l Closed-loop gain can achieve 10b accuracy with low DC gain A of 30dB. 15 NTUEE ; Mixed-Signal IC Lab 陳信樹 Self-Calibrated Algorithm (1) l Self-calibrated procedure starts with the last stage MDAC. l After MDAC is calibrated, it is treated as “ideal” MDAC. l Ideal MD
