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1、Maximum delay: tpLH=tpHL=15 ns tp = 3tpLH + 3tpHL = 315 + 315 = 90 ns 6. 9 74LS00: 6.20 (a) 6.20 (b) F 6.20 (b) A C B (c) D C B A VCC F (d) W VCC Z Y X Z Y X F (e) F G Y X W VCC (f) C B A C E D F G 6.21 Both halves of the 139 are enabled simultaneously when EN_L is asserted. Therefore, two three-sta
2、te drivers will be enabled to drive SDATA at the same time. Perhaps the designer forgot to put an extra inverter on the signal going to 1G or 2G, which would ensure that exactly one source drives SDATA at all times. 6.38 十进制译码器的设计 输入：四位 D、C、B、A，BCD码 输出：十位 Y0Y9，十中取一码 DCBAY0Y1Y2Y3Y4Y5Y6Y7Y8Y9 0 0 0 01
3、000000000 0 0 0 10100000000 0 0 1 00010000000 0 0 1 10001000000 1 0 0 10000000001 1 0 1 0dddddddddd dddddddddd 1 1 1 1dddddddddd Y0,Y1需要4个输入,Y2-Y7需要3个输入,Y8-Y9需要2个输入 2个4输入的与门，6个3输入的与门，2个2输入的与门 4-16译码器的设计,去除其中的6个输出 DCBAY0Y1Y2Y3Y4Y5Y6Y7Y8Y9 0 0 0 01000000000 0 0 0 10100000000 0 0 1 00010000000 0 0 1 10
4、001000000 1 0 0 10000000001 1 0 1 00000000000 0000000000 1 1 1 10000000000 BA DC 00 01 11 10 00 01 11 10 0 1 2 3 4 5 6 7 8 9 10个4输入的与门 6.41 专用译码器的设计 输入：A2、A1、A0，使能信号CS_L 输出：8个信号 6.43使用一个SSI和一个74x138完成下列函数 SSI器件：P.361 图6-18 6.51 16-4编码器 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0
5、1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 I15 I14 I8 I7 I1 I0Y3 Y2 Y1 Y0 Y3=I15+I14+I8 Y2=I15+I14+I13+I12+I7+I6+I5+I4 Y1=I15+I14+I11+I10+I7+I6+I3+I2 Y0=I15+I13+I1 用与非门实现: Y3=I15_L+I14_L+I8_L Y2=I15_L+I14_L+I13_L+ I12_L+ I7_L+I6_L+ I5_L+I4_L Y1=I15_L+I14_L+I11_L+ I10L+I7_L+I6_L+ I3_L+I2_L Y0=I15_L+I13_L+I1_L 6.63 设计3输入5位的多路复用器（24引脚 ） 输入、输出端口数分配 D0: 1D05D0 D1: 1D15D1 D2: 1D25D2 6.65 设计4输入18位的多路复用器 S2S1S0 INPUT to SELECT 0 0 0A 0 0 1B 0 1 0A 0 1 1C 1 0 0A 1 0 1D 1 1 0A 1 1 1B 所有的C,B,A端口都分别连到 S2,S1,S0
