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1、数字电路设计讲座必须掌握的技能u 如何运用Verilog HDL语言进行电路设计u 怎样实现层次化/结构化设计u 怎样编写测试激励（test_bench）u 怎样调试电路代码和进行电路仿真（Debbusy、Modelsim）（一）verilog语言简介（通过几个实例来说明）1，帧头检测电路moduleframe_head_detect (clk, reset, cout, cin);input clk, reset, cin;output cout;reg 7:0 temp;always (posedge clk or posedge reset)if (reset)temp = 8b0;el
2、setemp = temp7:0, cin;assigncout = (temp=8b01111110);endmodule说明：1，电路模块以module开始，以endmodule结束。 2，电路模块由名称、端口信号、端口信号说明、程序体等组成。3，程序体由中间信号、语句等组成。4，语句主要有always和assign语句。边沿触发和电平触发。5，信号有wire和reg（register）之分。它们可以互换，没有本质区别。6，改写temp = temp7:0, cin;7，改写assigncout = (temp=8b01111110);2，查找表电路modulerom_data8 (add
3、r, data, parity);input2:0 addr;output 3:0data; output parity; reg4:0mem 0:7;wire4:0data_temp;assign data_temp = memaddr;assigndata = data_temp4:1;assignparity = data_temp0;initial $readmemh(D:/rom_cof.hex, mem);endmodule问题：在这个模块中，data_temp定义为wire，所以用assign语句赋值，如何改成always语句的赋值方式？3，随机数产生器发送和接收电路/*/fil
4、e: prbs15_tx.v/ functions:Complete prbs15 transmit function./author:Yao Yafeng/version 1.0 2010-09-12 /*moduleprbs15_tx(/inputreset,clk2m,phaseinv,/outputprbsdata);Inputreset;Inputclk2m;Inputphaseinv; /测试码反相使能，1表示发送码流反相Outputprbsdata;/产生15位的M序列Reg14:0shift_buf;always (posedge clk2m or posedge reset)
5、 if(reset) shift_buf=15b100100100000000;/设定初始值 elsebegin shift_buf0=shift_buf13shift_buf14;/15级M序列编码规则 shift_buf1 = shift_buf0; shift_buf2 = shift_buf1; shift_buf3 = shift_buf2; shift_buf4 = shift_buf3; shift_buf5 = shift_buf4; shift_buf6 = shift_buf5; shift_buf7 = shift_buf6; shift_buf8 = shift_buf
6、7; shift_buf9 = shift_buf8; shift_buf10 = shift_buf9; shift_buf11 = shift_buf10; shift_buf12 = shift_buf11; shift_buf13 = shift_buf12; shift_buf14 = shift_buf13; end regdatatmp;always (posedge clk2m or posedge reset) if (reset) datatmp = #1 0;else datatmp = #1 shift_buf14;wireprbsdatatmp;assignprbsd
7、atatmp=(phaseinv)? (!datatmp):datatmp;regprbsdata;always (posedge clk2m or posedge reset) if (reset) prbsdata = #1 0; else prbsdata = #1 prbsdatatmp;endmodule/*/file: prbs15_rx.v/functions:Complete prbs15 received function./ /*module prbs15_rx(/inputreset,datain,clkin,reset_errcnth,reset_errcntl,/ou
8、tputtestLOP,testAIS,errcodecntl,errcodecnth);inputreset;Inputdatain;Inputclkin;Inputreset_errcnth;Inputreset_errcntl;outputtestLOP;outputtestAIS;output7:0errcodecntl;output7:0errcodecnth;/产生15位的移位接收寄存器reg14:0shift_buf;always (posedge clkin or posedge reset) if(reset) shift_buf=15b0;/设定初始值 elsebegin
9、shift_buf0= datain;shift_buf1 = shift_buf0; shift_buf2 = shift_buf1; shift_buf3 = shift_buf2; shift_buf4 = shift_buf3; shift_buf5 = shift_buf4; shift_buf6 = shift_buf5; shift_buf7 = shift_buf6; shift_buf8 = shift_buf7; shift_buf9 = shift_buf8; shift_buf10 = shift_buf9; shift_buf11 = shift_buf10; shi
10、ft_buf12 = shift_buf11; shift_buf13 = shift_buf12; shift_buf14 = shift_buf13; end wiresyn_en;/同步使能assignsyn_en=(shift_buf = 15b100100100000000);/产生15位的缺省M序列reg14:0shift_buf2;always (posedge clkin or posedge syn_en) if(syn_en) shift_buf2=15b100100100000000;/设定初始值 elsebegin shift_buf20=shift_buf213shi
11、ft_buf214;/15级M序列编码规则 shift_buf21 = shift_buf20; shift_buf22 = shift_buf21; shift_buf23 = shift_buf22; shift_buf24 = shift_buf23; shift_buf25 = shift_buf24; shift_buf26 = shift_buf25; shift_buf27 = shift_buf26; shift_buf28 = shift_buf27; shift_buf29 = shift_buf28; shift_buf210 = shift_buf29; shift_buf211 = shift_buf210; shift_buf212 = shift_buf211; shift_buf213 = shift_buf212; shift_buf214 = shift_buf21
