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1、 MCS9901 PCB Layout PCB Layout GuideLines Guidelines 1.Introduction As system operation speeds are increasing, PCB layout is becoming increasingly complex. A successful high-speed layout / PCB need to integrate the ICs and other peripherals / components effectively into a single design. MCS9901 has
2、PCIe, Serial, Parallel, ISA System designers must be careful in handling these issues during PCB layout design. This document provides generic layout guidelines for MCS9901 based products. PCIe to 4 Serial evaluation board design used as an example to detail the guidelines below. 2. PCB Overview 2.1
3、.1. PCB Details Figure 1a is the Top side of the MCS9901 4Serial Board. Most of the components are placed on the Top side of the PCB. Supply decoupling capacitors used on the bottom side to arrive at small form factor. Customers wishing to have components only of top side for process & cost reasons
4、can do so, with appropriate layout. Figure 1a - Top Side View of MCS9901-4S-EVB Rev1.1 Preliminary - 1 - 26th Nov 2007 MCS9901 PCB Layout PCB Layout GuideLines Guidelines Figure 1b Top Side View - Component Placement MCS9901-4S-EVB 2.2 Components Placement A. MCS9901 ASIC B. 12 MHz CRYSTAL C. SERIAL
5、 PORTS Rev1.1 Preliminary - 2 - 26th Nov 2007 MCS9901 PCB Layout PCB Layout GuideLines Guidelines 3.Layout Guidelines This layout guide discusses the important issues and provide guidelines for successful, effective pcb designs using MCS9901. PCIe_REFCLKP & PCIe_REFCLKN, PCIe_TXP & PCIe_TXN, PCIe_RX
6、P & PCIe_RXN are the 3 differential pairs to be routed from PCIe edge connector to MCS9901 ASIC with 100 Ohms differential Impedance. USB-DP & USB-DM are differential pairs to be routed with 90 Ohms differential Impedance, this rule to be applied for USB flavor of MCS9901 EVB. General layout guideli
7、nes 3.1.1. PCIe , USB & Generic Layout Guidelines MCS9901 Placement and PCIe Routing Guidelines Place the MCS9901 ASIC as close as to the PCIe connector on the board as shown in Figure 1b. Keep parallelism between PCIe_REFCLKP & PCIe_REFCLKN, PCIe_TXP & PCIe_TXN, and PCIe_RXP & PCIe_RXN with the tra
8、ce spacing, common trace width / lengths to achieve 100 Ohms differential impedance. Route the High Speed signals like Clock, PCIe_REFCLKP & PCIe_REFCLKN, PCIe_TXP & PCIe_TXN, PCIe_RXP & PCIe_RXN signals as equal and minimum possible trace lengths. Keep the maximum route spacing between PCIe signals
9、 and other signals. PCIe specification recommends the maximum trace length of PCIe differential signals to be less than 3.5 inches (i.e from PCIe edge connector to the pin / pad of PCIe controller ASIC) and a maximum of 4 Vias per differential pair. For more details refer to PCIe 1.0a Specification
10、& layout guidelines of PCI SIG. Route the PCIe differential signals, on the Top side or Bottom side of the PCB, which is adjacent to the ground plane layer. Avoid plane splits under these high speed signals in the layout. Rev1.1 Preliminary - 3 - 26th Nov 2007 MCS9901 PCB Layout PCB Layout GuideLine
11、s Guidelines USB Placement and Routing Guidelines Place the USB type-A connector and ESD Suppressors Inductor as close as possible on the USB interface pins of MCS9901 ASIC. Keep parallelism between DP and DM with the trace spacing, which achieves 90 Ohms differential impedance. Route the High Speed
12、 signals like Clock and DP & DM USB signals as equal and minimum possible trace lengths. Keep the maximum possible route spacing between USB signals and other signals. Route the USB Differential signals DP & DM, on the Top side or Bottom side of the PCB, which is adjacent to the ground plane layer.
13、Avoid plane splits under these high speed signals on the layout. For more details please refer to the USB2.0 Specification & layout guidelines recommended for High Speed USB by USB-IF Forum. Generic routing guidelines When it becomes necessary to turn the trace by 90, use to 45 turns or an arc inste
14、ad of making a single 90 turn. This reduces reflections on the signal by minimizing impedance discontinuities. Do not route PCIe / USB traces under crystal oscillator, clock-synthesizers, magnetic devices or ICs that use and/or duplicate clocks. Use minimum possible Vias on differential signal trace
15、s and routing these signals too close to crossing the split ground plane will adversely affect the differential trace impedance. Rev1.1 Preliminary - 4 - 26th Nov 2007 MCS9901 PCB Layout PCB Layout GuideLines Guidelines Stubs on differential signal pair should be avoided. When stubs exist, it will cause signal reflection and affect signal quality. If a stub is unavoidable in the design, no stub should be greater than 200mils. Route differential signal pair traces over continuous ground or power planes. Avoid cross
