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1、- 1 - K4B4G1646Q Rev. 0.5, Apr. 2013 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an “AS IS“ basis, without warra
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3、mplication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any government
4、al procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ?2013 Samsung Electronics Co., Ltd. All rights re
5、served. Preliminary 4Gb Q-die DDR3L SDRAM Olny x16 96FBGA with Lead-Free this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single- ended components of differential signals the requirement to reach VSELmax, VSEHmin has no beari
6、ng on timing, but adds a restriction on the common mode characteristics of these signals. Table 14 Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU NOTE : 1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VI
7、L(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need
8、to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specification“ SymbolParameter DDR3-800/1066/1333/1600 UnitNOTE MinMax VSEH Single-ended high-level for strobes(VDD/2)+0.1
9、75NOTE3V1, 2 Single-ended high-level for CK, CK(VDD/2)+0.175NOTE3V1, 2 VSEL Single-ended low-level for strobesNOTE3(VDD/2)-0.175V1, 2 Single-ended low-level for CK, CKNOTE3(VDD/2)-0.175V1, 2 VDD or VDDQ VSEH min VDD/2 or VDDQ/2 VSEL max VSEH VSS or VSSQ VSEL CK or DQS time - 17 - datasheetK4B4G1646Q
10、DDR3L SDRAM Rev. 0.5Preliminary 8.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below tabl
11、e. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS. Figure 3. VIX Definition Table 15 Cross point voltage for differential input signals (CK, DQS) : 1.35V NOTE : 1. The relationbetween Vix Mi
12、n/Max and VSEL/VSEH should satisfy following. (VDD/2) + Vix(Min) - VSEL 25mV VSEH - (VDD/2) + Vix(Max) 25mV Table 16 Cross point voltage for differential input signals (CK, DQS) : 1.5V NOTE : 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are mo
13、notonic, have a single-ended swing VSEL / VSEH of at least VDD/2 250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. SymbolParameter DDR3L-800/1066/1333/1600 UnitNOTE MinMax VIXDifferential Input Cross Point Voltage relative to VDD/2 for CK,CK-150150mV1 VIXDifferential Input Cros
14、s Point Voltage relative to VDD/2 for DQS,DQS-150150mV SymbolParameter DDR3-800/1066/1333/1600 UnitNOTE MinMax VIXDifferential Input Cross Point Voltage relative to VDD/2 for CK,CK -150150mV -175175mV1 VIXDifferential Input Cross Point Voltage relative to VDD/2 for DQS,DQS-150150mV VDD CK, DQS VDD/2
15、 CK, DQS VSS VIX VIX VIX - 18 - datasheetK4B4G1646QDDR3L SDRAM Rev. 0.5Preliminary 8.5 Slew rate definition for Differential Input Signals See 14.3 “Address/Command Setup, Hold and Derating :” on page 50 for single-ended slew rate definitions for address and command signals. See 14.4 “Data Setup, Ho
16、ld and Slew Rate Derating :” on page 56 for single-ended slew rate definitions for data signals. 8.6 Slew rate definitions for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 17 and Figure 4. Table 17 Differential input slew rate definition NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds. Figure 4. Differential Input Slew Rate definition
