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1、1,程序處理與狀態機電路設計,第九章,儒林圖書公司 TB061,VHDL數位電路設計實務教本使用Quartus II,Case-when敘述指令,2,Case-when指令本身是敘述組合邏輯的，但它卻必須在Process指令中執行，因此它是序向邏輯指令之一 ,其語法如下:,Case 選擇訊號 IS When 選擇訊號1 = 敘述命令1; When 選擇訊號2 = 敘述命令2; : When Others = 敘述命令N;End Case;,Case-when敘述指令Example:四對一的多工器設計,3,library IEEE;use IEEE.STD_LOGIC_1164.all; ENT
2、ITY mux4to1_case ISPORT ( S : IN STD_LOGIC_VECTOR(1 downto 0); D0,D1,D2,D3 : IN STD_LOGIC; Y :OUT STD_LOGIC );END mux4to1_case;,ARCHITECTURE a OF mux4to1_case ISBEGIN process(S) Begin Case S IS When 00= Y Y Y Y=D3; End Case; End Process;END a;,Case-when敘述指令Example:一對四的解多工器設計,4,library IEEE;use IEEE.
3、STD_LOGIC_1164.all; ENTITY demux1to4_case ISPORT ( data : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 downto 0); D0,D1,D2,D3 : OUT STD_LOGIC);END demux1to4_case;,ARCHITECTURE a OF demux1to4_case ISBEGIN process(S,data) Begin D0=0;D1=0; D2=0;D3 D0 D1 D2 D3=data; End Case; End Process;END a;,Case-when敘述指令
4、Example:JK正反器設計,5,library ieee;use ieee.std_logic_1164.all;entity JK_ff isport (clk :in std_logic; J, K :in std_logic; rst :in std_logic; Q, Qbar:out std_logic);end JK_ff; architecture a of JK_ff issignal temp : std_logic;signal x : std_logic_vector(1 downto 0);begin x = J & K;,process(clk, rst) beg
5、inif (rst=1) then temp temp temp temp null; end case;end if; end process; Q = temp; Qbar F F F F F F F F F F F F F=Not A; END case;,IF Sel(0)=1 THEN ALU_output= F(6 downto 0) & 0; ELSE ALU_output present_state:=101; WHEN 101 = present_state:=110; WHEN 110 = present_state:=100; WHEN 100 = present_sta
6、te:=011; WHEN 011 = present_state:=010; WHEN 010 = present_state:=000; WHEN OTHERS= present_state:=000;END CASE; end if; op= present_state;END PROCESS;END a;,ENTITY moore_3 ISPORT( CLK :IN STD_LOGIC; OP:OUT std_logic_vector(2 downto 0);END moore_3;,Assignment statement,Variable name,狀態機(State Machine)電路設計Example:計數器設計,11,ARCHITECTURE a OF moore_ss ISsignal op: std_logic_vector(2 downto 0);BEGINPROCESS(clk) BEGIN IF reset=1 then op op op op op op =001; ENDCASE; end if;END PROCESS;z=op;END a;,
