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1、CSE 370 - Spring 1998 - Verilog for Sequential Systems - 1,Today: Verilog and Sequential Logic,Flip-flops representation of clocks - timing of state changes asynchronous vs. synchronous FSMs structural view (FFs separate from combinational logic) behavioral view (synthesis of sequencers) Sequential
2、dont cares,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 2,module dff (CLK, d, q); input CLK, d; output q; reg q; always (CLK) q = d; endmodule,Incorrect Flip-flop in Verilog,Use always blocks sensitivity list to wait for clock to change,Not correct! Q will change whenever the clock chang
3、es, not just on the edge.,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 3,module dff (CLK, d, q); input CLK, d; output q; reg q; always (posedge CLK) q = d; endmodule,Correct Flip-flop in Verilog,Use always blocks sensitivity list to wait for clock edge,CSE 370 - Spring 1998 - Verilog for
4、 Sequential Systems - 4,module dff (CLK, s, r, d, q); input CLK, s, r, d; output q; reg q; always (posedge CLK) if (r) q = 1b0; else if (s) q = 1b1; else q = d; endmodule,module dff (CLK, s, r, d, q); input CLK, s, r, d; output q; reg q; always (posedge r) q = 1b0; always (posedge s) q = 1b1; always
5、 (posedge CLK) q = d; endmodule,More Flip-flops,Synchronous/asynchronous reset/set single thread that waits for the clock three parallel threads only one of which waits for the clock,Synchronous,Asynchronous,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 5,Example: A parity checker,Serial
6、input string OUT=1 if odd # of 1s in input OUT=0 if even # of 1s in input,Present Input Next Present State State Output,Even 0 Even 0 Even 1 Odd 0 Odd 0 Odd 1 Odd 1 Even 1,1. State diagram and state-transition table,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 6,Example: A parity checker
7、 (continued),2. State minimization: Already minimized Need both states (even and odd) Use one flip-flop 3. State assignment (or state encoding),Present Input Next Present State State Output,0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 7,Example: A parity c
8、hecker (continued),4. Next-state logic minimization Assume D flip-flops Next state = (present state) XOR (present input) Present output = present state 5. Implement the design,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 8,module FSM (CLK, in, out); input CLK; input in; output out; reg o
9、ut; / state variable reg 1:0 state; / local variable reg 1:0 next_state; always (posedge CLK) / registers state = next_state; always (state or in) / Compute next-state and output logic whenever state or inputs change. / (i.e. put equations here for next_state1:0) / Make sure every local variable has
10、 an assignment in this block! endmodule,Verilog Structural View of a FSM,General view of a finite state machine in verilog,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 9,define zero 0 define one1 1 define two1s 2 module reduce (CLK, reset, in, out); input CLK, reset, in; output out; reg
11、out; reg 1:0 state; / state variables reg 1:0 next_state; always (posedge CLK) if (reset) state = zero; else state = next_state;,state assignment,Moore Verilog FSM,Reduce 1s example,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 10,always (in or state) case (state) zero: / last input was a
12、 zero begin if (in) next_state = one1; else next_state = zero; end one1: / weve seen one 1 begin if (in) next_state = two1s; else next_state = zero; end two1s: / weve seen at least 2 ones begin if (in) next_state = two1s; else next_state = zero; end endcase,crucial to include all signals that are in
13、put to state and output equations,Moore Verilog FSM (continued),note that output only depends on state,always (state) case (state) zero: out = 0; one1: out = 0; two1s: out = 1; endcase endmodule,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 11,module reduce (CLK, reset, in, out); input CL
14、K, reset, in; output out; reg out; reg state; / state variables reg next_state; always (posedge CLK) if (reset) state = zero; else state = next_state; always (in or state) case (state) zero: / last input was a zero begin out = 0; if (in) next_state = one; else next_state = zero; end one: / weve seen
15、 one 1 if (in) begin next_state = one; out = 1; end else begin next_state = zero; out = 0; end endcase endmodule,Mealy Verilog FSM,Input,Remember the Highlight- The-Arrows Method,Output,CSE 370 - Spring 1998 - Verilog for Sequential Systems - 12,always (posedge CLK) begin temp = B; B = A; A = temp; end,always (posedge CLK) begin A = B; B = A; end,Blocking and Non-Blocking Assignments,Blocking assignments (X=A) completes the assignment b
