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1、Sequential Logic Test1.1 INTRODUCTION The previous chapter examined methods for creating sensitized paths in combina- tional logic extending from stuck-at faults on logic gates to observable outputs. We now attempt to create tests for sequential circuits where the outputs are a function not just of
2、present inputs but of past inputs as well. The objective will be the same: to create a sensitized path from the point where a fault occurs to an observable out- put. However, there are new factors that must be taken into consideration. A sensi- tized path must now be propagated not only through logi
3、c operators, but also through an entirely new dimensiontime. The time dimension may be discrete, as in synchronous logic, or it may be continuous, as in asynchronous logic. The time dimension was ignored when creating tests for faults in combinational logic.It was implicitlyassu med that the output
4、response would stabilize before being measured with test equipment, and it was generally assumed that each test pat- tern was independent of its predecessors. As will be seen, the effects of time cannot be ignored, because this added dimension greatly inuences the results of test pat- tern generatio
5、n and can complicate, by orders of magnitude, the problem of creating tests. Assumptions about circuit behavior must be carefully analyzed to determine the circumstances under which they prevail. 1.2 TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC Two factors complicate the task of creating tests for seque
6、ntial logic: memory and circuit delay. In sequential circuits the signals must not only be logically correct, but must also occur in the correct time sequence relative to other signals. The test prob- lem is further complicated by the fact that aberrant behavior can occur in sequential circuits when
7、 individual discrete components are all fault-free and conform to their manufacturers specications. We rst consider problems caused by the presence of memory, and then we examine the effects of circuit delay on the test generation problem.1.2.1 The Effects of Memory In the rst chapter it was pointed
8、 out that, for combinational circuits, it was possible (but not necessarily reasonable) to create a complete test for logic faults by applying all possible binary combinations to the inputs of a circuit. That, as we shall see, is not true for circuits with memory. They may not only require more than
9、 2 tests, but are also sensitive to the order in which stimuli are applied. Test Vector Ordering The effects of memory can be seen from analysis of the cross-coupled NAND latch cf. Figure 2.3(b). Four faults will be considered, these being the input SA1 faults on each of the two NAND gates (numberin
10、g is from top to bottom in the diagram). All four possible binary combinations are applied to the inputs in ascending orderthat is, in the sequence (Set, Reset) = (0,0), (0,1), (1,0), (1,1). We get the following response for the fault-free circuit (FF) and the circuit corresponding to each of the fo
11、ur input SA1 faults. Input Output Set Reset FF 1 2 3 40 0 1 0 1 1 10 1 1 0 1 1 11 0 0 0 0 0 11 1 0 0 0 1 1In this table, fault number 2 responds to the sequence of input vectors with an output response that exactly matches the fault-free circuit response. Clearly, this sequence of inputs will not di
12、stinguish between the fault-free circuit and a circuit with input 2 SA1.The sequence is now applied in the exact opposite order. We get:Input OutputSet Reset FF 1 2 3 41 1 ? ? 0 1 ?1 0 0 0 0 0 ?0 1 1 0 1 1 10 0 1 0 1 1 1The Indeterminate Value When the four input combinations are applied in reverse
13、order, question marks appear in some table positions. What is their signi- cance? To answer this question, we take note of a situation that did not exist when dealing only with combinational logic; the cross-coupled NAND latch has memory. By virtue of feedback present in the circuit, it is able to r
14、emember the value of a sig- nal that was applied to the set input even after that signal is removed. Because of the feedback, neither the Set nor the Reset line need be held low any longer than necessary to effectively latch the circuit. However, when power is rst applied to the circuit, it is not known what value is contained in the latch. How can circuit behavior be simulated when it is not known what value is contained in its memory? In real circuits, memory elements such as latches and ip-op
