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1、1Analog to Digital ConversionADC EssentialsADC EssentialsA/D Conversion TechniquesA/D Conversion TechniquesInterfacing the ADC to the IBM PCInterfacing the ADC to the IBM PCDAS (Data Acquisition Systems)DAS (Data Acquisition Systems)How to select and use an ADCHow to select and use an ADCA low cost
2、DAS for the IBM PCA low cost DAS for the IBM PCChap 02Why ADC ?nDigital Signal Processing is more popularuEasy to implement, modify, uLow costnData from real world are typically AnalognNeeds conversion system ufrom raw measurements to digital datauConsists ofFAmplifier, FiltersFSample and Hold Circu
3、it, MultiplexerFADCChap 03ADC EssentialsnBasic I/O RelationshipuADC is Rationing SystemFx = Analog input / ReferenceFraction: 0 1nn bits ADCuNumber of discrete output level : 2nuQuantumFLSB sizeFQ = LSB = FS / 2nnQuantization Erroru1/2 LSBuReduced by increasing nChap 04Converter ErrorsnOffset Errorn
4、Gain ErrornCan be eliminated by initial adjustmentsnIntegral Linearity ErrornDifferential Linearity ErrornNonlinear ErroruHard to removeChap 05TerminologiesnConverter ResolutionuThe smallest change required in the analog input of an ADC to change its output code by one levelnConverter AccuracyuThe d
5、ifference between the actual input voltage and the full-scale weighted equivalent of the binary output codeuMaximum sum of all converter errors including quantization errornConversion TimeuRequired time (tc) before the converter can provide valid output datanConverter Throughput RateuThe number of t
6、imes the input signal can be sampled maintaining full accuracyuInverse of the total time required for one successful conversionuInverse of Conversion time if No S/H(Sample and Hold) circuit is usedChap 06More on Conversion TimenInput voltage change during the conversion process introduces an undesir
7、able uncertaintynFull conversion accuracy is realized only if this uncertainty is kept low below the converters resolutionuRate of Change x tc resolutionu nExampleu8-bit ADCuConversion Time: 100secuSinusoidal inputF FRate of change FLet FS = 2AuLimited to Low frequency of 12.4 HzFFew ApplicationsCha
8、p 07S/H increase PerformancenS/H (Sample and Hold)uAnalog circuits that quickly samples the input signal on command and then holds it relatively constant while the ADC performs conversionuAperture time (ta)FTime delay occurs in S/H circuits between the time the hold command is received and the insta
9、nt the actual transition to the hold mode takes placeFTypically, few nsecnExampleu20 nsec aperture timeF FReasonably good for 100sec converterChap 08Analog Input SignalnTypically, Differential or Single-ended input signal of a single polarityuTypical Input RangeF0 10V and 0 5VuIf Actual input signal
10、 does not span Full Input rangeFSome of the converter output code never usedFWaste of converter dynamic rangeFGreater relative effects of the converter errors on outputnMatching input signal and input rangeuPrescaling input signal using OP AmpFIn a final stage of preconditioning circuituBy proportio
11、nally scaling down the reference signalFIf reference signal is adjustableChap 09Converting bipolar to unipolarnUsing unipolar converter when input signal is bipolaruScaling down the inputuAdding an offsetnBipolar ConverteruIf polarity information in output is desireduBipolar input rangeFTypically, 0
12、 5VuBipolar OutputF2s ComplementFOffset BinaryFSign MagnitudeFnInput signal is scaled and an offset is addedscaledAddoffsetChap 010Outputs and Analog Reference SignalnI/O of typical ADCnADC outputuNumber of bitsF8 and 12 bits are typicalF10, 14, 16 bits also availableuTypically natural binaryFBCD (3
13、 BCD)For digital panel meter, and digital multimeternErrors in reference signaluFromFInitial AdjustmentFDrift with time and temperatureuCauseFGain error in Transfer characteristicsnTo realize full accuracy of ADCuPrecise and stable reference is crucialFTypically, precision IC voltage reference is us
14、ed5ppm/C 100ppm/CChap 011Control SignalsnStartuFrom CPUuInitiate the conversion processnBUSY / EOCuTo CPUuConversion is in progressF0=Busy: In progressF1=EOC: End of ConversionnHBE / LBEuFrom CPUuTo read Output word after EOCFHBEHigh Byte EnableFLBELow Byte EnableChap 012A/D Conversion TechniquesnCo
15、unter or Tracking ADCnSuccessive Approximation ADCuMost Commonly UsednDual Slop Integrating ADCnVoltage to Frequency ADCnParallel or Flash ADCuFast ConversionnSoftware ImplementationnShaft EncoderChap 013Counter Type ADCnBlock diagramnWaveformnOperationuReset and Start CounteruDAC convert Digital ou
16、tput of Counter to Analog signaluCompare Analog input and Output of DACFVi VDACContinue countingFVi = VDACStop countinguDigital Output = Output of CounternDisadvantageuConversion time is variedF2n Clock Period for Full Scale inputChap 014Tracking Type ADCnTracking or Servo TypeuUsing Up/Down Counter
17、 to track input signal continuouslyFFor slow varying inputnCan be used as S/H circuituBy stopping desired instantuDigital OutputuLong Hold TimenDisabling UP (Down) control, Converter generateuMinimum (Maximum) value reached by input signal over a given periodChap 015Successive Approximation ADCnMost
18、 Commonly used in medium to high speed ConvertersnBased on approximating the input signal with binary code and then successively revising this approximation until best approximation is achievednSAR(Successive Approximation Register) holds the current binary valuenBlock DiagramChap 016Successive Appr
19、oximation ADCnCircuit waveformnLogic FlownConversion Timeun clock for n-bit ADCuFixed conversion timenSerial Output is easily generateduBit decision are made in serial orderChap 017Dual Slope Integrating ADCnOperationuIntegrateuReset and integrateuThusunApplicationsuDPM(Digital Panel Meter), DMM(Dig
20、ital Multimeter), nExcellent Noise RejectionuHigh frequency noise cancelled out by integrationuProper T1 eliminates line noiseuEasy to obtain good resolutionnLow SpeeduIf T1 = 60Hz, converter throughput rate 30 samples/sChap 018Voltage to Frequency ADCnVFC (Voltage to Frequency Converter)uConvert an
21、alog input voltage to train of pulsesnCounteruGenerates Digital output by counting pulses over a fixed interval of timenLow SpeednGood Noise ImmunitynHigh resolutionuFor slow varying signaluWith long conversion timenApplicable to remote data sensing in noisy environmentsuDigital transmission over a
22、long distanceChap 019Parallel or Flash ADCnVery High speed conversionuUp to 100MHz for 8 bit resolutionuVideo, Radar, Digital OscilloscopenSingle Step Conversionu2n 1 comparatoruPrecision Resistive NetworkuEncodernResolution is limiteduLarge number of comparator in ICnHomework #5-1u .Chap 020Softwar
23、e ImplementationnImplementation with software using microprocessoruCountinguShiftinguInvertinguCode ConversionunLimited Practical UseuAvailability of Good performance with very reasonable CostChap 021Shaft EncodernElctromechanical ADCuConvert shaft angle to digital outputnEncodinguOptical or Magneti
24、c SensornApplicationsuMachine tools, Industrial robotics, Numerical controlnBinary EncoderuMisalignment of mechanism causes large errorFEx: 011 111 (180deg)nGray EncoderuMisalignment causes 1 LSB errorChap 022Interfacing the ADC to the IBM PCnInterface OperationsuMost-recent-data SchemeFAt end of co
25、nversion it updates an output FIFOFAutomatically start new conversionFCPU read FIFO to acquire most recent datauStart-and-wait SchemeFCPU initiate conversion every time it needs new dataFCPU check EOC until conversion is finisheduUsing CPU InterruptFCPU initiate conversion every time it needs new da
26、taFCPU can proceed to do other thingFADC interrupt CPU when conversion is completeFCPU goes to ISRuSee Chapter 3, For more information about 8259AChap 023Interface SoftwarenMemory Mapped TransfersuADC is assigned in Memory SpaceFMRD, MWR signalFMOV instructionuMore complex decoding logicnI/O Mapped
27、TransfersuADC is in I/O SpaceFIOR, IOW signalFIN, OUT instructionuMore Simple decoding logicnDMA (Direct Memory Access)uCPU release system bus by the request of DMAuDMA controller carried out data transfer by generating the required addresses and control signalsuThe system bus control reverts back t
28、o CPU when data transfer is finishednDMA is usefuluHigh SpeeduHigh volume data transferFDisk Drive interfaceChap 024Interface HardwarenParallel Data FormatuThree state output buffer in ADCuTo Interface ADCFCPU + Decoding logicTo generate Chip Select signalTo generate Start SignalTo Check EOC signaln
29、Serial Data FormatuAsynchronous Serial transmission to send data over long distance to a monitoring stationFUART is commonly usednInterfacing 10 or 12 bit ADCuTransfer data in chunks of 8 bits one after anotherChap 025DAS (Data Acquisition System)nDAS performs the complete function of converting the
30、 raw outputs from one or more sensors into equivalent digital signals usable for further processing, control, or displaying applicationsnApplicationsuSimple monitoring of a single analog variableuControl and Monitoring of hundreds of parameters in a nuclear plantChap 026Single Channel SystemnTransdu
31、ceruGenerate signal of low amplitude, mixed with undesirable noisenAmplifier, FiltersuAmplifyuRemove noiseuLinearizenS/H (Sample and Hold)uReduce uncertainty error in the converted output when input changes are fast compared to the conversion timeuIn Multi-channel systemFTo hold a sample from one ch
32、annel while multiplexer proceed to sample next oneFSimultaneous sampling of two signalChap 027Sample and Hold CircuitsnCare in selecting hold capacitor ChuLow ValueFReduces acquisition timeFIncrease DroopuHigh ValueFMinimize DroopFIncrease acquisition timeuChoose capacitor to get a best acquisition
33、time while keeping the droop per conversion below 1 LSBChap 028Commercially Available S/HChap 029Multi-channel SystemnAnalog multiplexer and a ADCuLow costnLocal ADCs and digital multiplexeruHigher sampling rateChap 030How to select and use an ADCnRange of commercially available ADCsnGuidelines for
34、using ADCsuUse the full input range of the ADCuUse a good source of reference signaluLook out for fast input signal changesuKeep analog and digital grounds separateuMinimize interference and loading problemChap 031Commercially available monolithic ADCsChap 032Commercially available hybrid ADCsChap 0
35、33A low cost DAS for the IBM PCnMulti-channel systemuLess than $100uADC0816 from National SemiconductoruConstant, repetitive rateF1000 samples/snGenerating clockuFor starting ADC conversionuFor causing interruptuMake a pulse stream from TCLK with short pulses of duration = x BCLK/4FTCLK from 8253 Ti
36、mer/CounterWide pulseChap 034ADC circuit for PC prototype boardSCSLCT(Start Conversion SeLeCT): Latched trough port 30CHSCSLCT = H Selection of 30AH (/E10) start conversionSCSLCT = L TCLK start conversionINTSLCT(INTerrupt SeLeCT): Latched trough port 30CHINTSLCT = H EOC cause IRQ2INTSLCT = L No Inte
37、rrupt CPU read Status register (Port 309H) to check EOCChap 035Status RegisternFor polling TCLK and EOC signalnPort 309H (/E9)nPolling of EOC results in a low level after the data from ADC have been readChap 036Throughput rate calculation4.77MHz / 8= 596KHzChap 037Accuracy CalculationnBetter than 1%
38、 accuracy is ensurednActual accuracy with smooth input signal at room temperature will be better than 0.5%Chap 038Basic Program for Controlling ADCSampling rate 200 samples/sBecause OUT and IN instruction in Basic takes 5msChap 039C Programming for Controlling ADCnSampling from ADC channel 1 at 5ms interval and sending each sampled data point to the DACChap 040Homework #5-2nPrototype board C program u Outp(CNTRL,5) .
