数字电子技术

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1、Figure 81 A 2-bit asynchronous binary counter. Open file F08-01 to verify operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 82 Timing diagram for the counter of Figure 81. As in previous chapters,

2、 output waveforms are shown in green. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 83 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F08-03 to verify operation. Th

3、omas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 84 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.

4、Upper Saddle River, New Jersey 07458All rights reserved.Figure 85 Four-bit asynchronous binary counter and its timing diagram. Open file F08-05 and verify the operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights res

5、erved.Figure 86 An asynchronously clocked decade counter with asynchronous recycling. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 87 Asynchronously clocked modulus-12 counter with asynchronous recyclin

6、g. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 88 The 74LS93 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.) Tho

7、mas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 89 Two configurations of the 74LS93 asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.) Thomas L. FloydDigital Fundament

8、als, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 810 74LS93 connected as a modulus-12 counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure

9、811 A 2-bit synchronous binary counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 812 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed

10、 to be equal). Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 813 Timing diagram for the counter of Figure 811. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle

11、 River, New Jersey 07458All rights reserved.Figure 814 A 3-bit synchronous binary counter. Open file F08-14 to verify the operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 815 Timing diagram for t

12、he counter of Figure 814. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 816 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded a

13、reas. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 817 A synchronous BCD decade counter. Open file F08-17 to verify operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education,

14、 Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 818 Timing diagram for the BCD decade counter (Q0 is the LSB). Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 819 The 74HC163 4-bit sync

15、hronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.) Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 820 Timing example for a 74HC163. Thomas L. FloydDigital F

16、undamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 821 The 74F162 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.) Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearso

17、n Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 822 Timing example for a 74F162. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 823 A basic 3-bit up/down synchronous counte

18、r. Open file F08-23 to verify operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 824 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 0

19、7458All rights reserved.Figure 825 The 74HC190 up/down synchronous decade counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 826 Timing example for a 74HC190. Thomas L. FloydDigital Fundamentals, 9eC

20、opyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 827 General clocked sequential circuit. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 828 State diag

21、ram for a 3-bit Gray code counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 829 Examples of the mapping procedure for the counter sequence represented in Table 87 and Table 88. Thomas L. FloydDigita

22、l Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 830 Karnaugh maps for present-state J and K inputs. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights

23、 reserved.Figure 831 Three-bit Gray code counter. Open file F08-31 to verify operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 832 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson

24、Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 833 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 834 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Educat

25、ion, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 835 State diagram for a 3-bit up/down Gray code counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 836 J and K maps for Table 8

26、11. The control input, Y, is treated as a fourth variable. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 837 Three-bit up/down Gray code counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by

27、Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 838 Two cascaded counters (all J and K inputs are HIGH). Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 839 Timing dia

28、gram for the cascaded counter configuration of Figure 838. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 840 A modulus-100 counter using two cascaded decade counters. Thomas L. FloydDigital Fundamentals,

29、 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 841 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide-by-10 and divide-by-100 outputs. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by

30、Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 842 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 843 A divide-by-100 counter using two 74F162 decade counters. Thoma

31、s L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 844 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is

32、the LSB in each counter). Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 845 Decoding of state 6 (110). Open file F08-45 to verify operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pears

33、on Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 846 A 3-bit counter with active-HIGH decoding of count 2 and count 7. Open file F08-46 to verify operation. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey

34、07458All rights reserved.Figure 847 A basic decade (BCD) counter and decoder. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 848 Outputs with glitches from the decoder in Figure 847. Glitch widths are exa

35、ggerated for illustration and are usually only a few nanoseconds wide. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 849 The basic decade counter and decoder with strobing to eliminate glitches. Thomas L

36、. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 850 Strobed decoder outputs for the circuit of Figure 849. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Je

37、rsey 07458All rights reserved.Figure 851 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 852 and 853. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserve

38、d.Figure 852 Logic diagram of typical divide-by-60 counter using 74F162 synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB). Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All righ

39、ts reserved.Figure 853 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 854 Function

40、al block diagram for parking garage control. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 855 Logic diagram for modulus-100 up/down counter for automobile parking control. Thomas L. FloydDigital Fundame

41、ntals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 856 Parallel-to-serial data conversion logic. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figur

42、e 857 Example of parallel-to-serial conversion timing for the circuit in Figure 856. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 858 The 74HC163 4-bit synchronous counter. Thomas L. FloydDigital Fundam

43、entals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 859 Example of a failure that affects following counters in a cascaded arrangement. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, Ne

44、w Jersey 07458All rights reserved.Figure 860 Example of a failure in a cascaded counter with a truncated sequence. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 861 Thomas L. FloydDigital Fundamentals, 9

45、eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 862 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 863 Traffic light control system block diagram.

46、Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 864 Sequence of traffic light states. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All

47、 rights reserved.Figure 865 Block diagram of the sequential logic. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 866 State diagram for the traffic light control system. Thomas L. FloydDigital Fundamental

48、s, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 867 Sequential logic diagram. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 868 Input logic fo

49、r the 2-bit Gray code counter. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 869 The sequential logic. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River,

50、New Jersey 07458All rights reserved.Figure 870 Block diagram of the complete traffic light control system. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 871 Comparison of asynchronous and synchronous cou

51、nters. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 872 Note that the labels (names of inputs and outputs) are consistent with text but may differ from the particular manufacturers data book you are usi

52、ng. The devices shown are functionally the same and pin compatible with the same device types in other available CMOS and TTL IC families. Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 873 Thomas L. Floy

53、dDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 874 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 875 Thomas L. FloydDigit

54、al Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 876 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 877 Thomas L. FloydDigital Fun

55、damentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 878 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 879 Thomas L. FloydDigital Fundament

56、als, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 880 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 881 Thomas L. FloydDigital Fundamentals, 9

57、eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 882 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 883 Thomas L. FloydDigital Fundamentals, 9eCopyr

58、ight 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 884 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 885 Thomas L. FloydDigital Fundamentals, 9eCopyright 2

59、006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 886 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 887 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by

60、 Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 888 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 889 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pears

61、on Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 890 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 891 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Edu

62、cation, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 892 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 893 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Figure 894 Thomas L. FloydDigital Fundamentals, 9eCopyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.