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1、面向二十一世纪的嵌入式系统设计技术第八讲：嵌入式项目开发过程Embedded System Project Management主讲教员：徐欣国防科大电子科学与工程学院嵌 入 式 系 统 开 放 研 究 小 组主要内容嵌入式设计生命周期选择过程划分决策详细的硬件与软件设计嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程开发、调试环境与工具嵌入式项目设计的各个阶段（图）嵌入式项目设计的七个具体阶段产品定义软件与硬件的划分迭代与实现详细的硬件与软件设计硬件与软件集成产品测试与发布持续维护与升级嵌入式项目开发过程中使用的工具参见PDF文档中的Figure 1.2嵌入式项目设计生命周期（一）产品
2、定义工程师追求卓越的功能和性能浪费时间和资源决策层早期一般不允许工程师接触客户损失了一些有用的建议和观点理想的客户研究访问首席：市场营销；第二成员：记录与提问其他技术人员：参与探讨并形成产品蓝图列出必做适宜清单，找到设计产品的共同蓝图嵌入式项目设计生命周期（二）硬件与软件的划分观点：软硬件是可以互相替换的如：浮点运算与浮点处理器（FPU）等两种不同的划分策略优化处理器能力和软件通过ASIC设计找到解决途径划分中需要考虑的许多需求价格低、性能领先、市场竞争、知识产权等CPU的选择将影响划分决策和开发工具选择嵌入式项目设计生命周期（三）迭代与实现迭代与实现阶段的主要特点：主要障碍可能还是在软硬件的
3、详细划分上设计约束被深刻理解和建模保留软硬件划分之间的余地软硬件设计人员之间的迭代结构体系模拟器：Simulator评估板或开发板：Evaluation Board目的：减小设计阶段后期风险嵌入式项目设计生命周期（四）详细的硬件与软件设计文档管理这里不详细讨论软硬件设计问题大部分同学在其他课程中学到的C/C+/JAVA编程技术、数字设计和微处理器知识使他们有足够的机会解决设计中遇到的问题文档管理与质量控制设计复用和可视化减小设计修改成本有助于测试和质量控制嵌入式项目设计生命周期（五）硬件与软件集成Not a easy ProblemBig Endian/Little Endian引发的问题调试
4、过程及实时系统调试方法带来的一些问题等嵌入式系统设计中软硬件集成的颠峰状态由第一个硬件原型、应用软件、驱动代码、操作系统设计出完美的系统没有致命错误没有飞线不用重新设计ASIC或FPGA没有太多的软件设计修改嵌入式项目设计生命周期（六）产品测试与发布嵌入式产品测试具有特殊的意义人们或许可以容忍PC偶然死机，但是核电站报警系统？！导弹控制系统？！PC外围硬件Is there any problem with you?测试的目的不仅是确信软件不会在关键时刻崩馈还必须查明是否在运行时能接近最优性能，尤其是用高级语言编写或多个开发人员编写的程序每个微小的错误都可能是致命的如轻微内存泄漏，长时间运行才能
5、发现的问题等嵌入式项目设计生命周期（七）产品维护和升级产品维护的模式维护/支持小组！设计小组维护详细文档经验技巧上一代产品产品升级的巨大代价理解原设计人员的思路与代码反向逆推并改进原始设计小组的工作需要非凡的技艺或强大的反向设计工具否则，不如开始新的设计，这是原供应商和生产上所不愿意看到的主要内容嵌入式设计生命周期选择过程划分决策详细的硬件与软件设计嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程开发、调试环境与工具选择过程处理器平台选择处理器是一个复杂的工作，它不仅是一个简单的“优化”问题，必须通过四道关键测试：是否便于实现是否能够提供足够的性能是否有合适的操作系统支持是否有大量合适的
6、开发工具（和设计资源）支持其他因素可能会影响这种选择上市时间、企业对特定开发商的偏好或承诺等How do we choose microprocessor ?Cost ofGoodsReal-timeConstraintsLegacyCodePowerBudgetPerformanceTime toMarketLandminesToolSupportClock SpeedBrute force method of improving performanceBottleneck could be in software design orcompiler !Faster isnt always
7、betterPerformance Clock speedTrade-off:As clock speedenergyMemory costs increaseOther peripheral devices will cost moreEvaluating processor performanceClock speed: but instructions per cycle may differInstructions/sec: but work per instruction maydifferDhrystone: Synthetic benchmark, developed in198
8、4SPEC: realistic benchmarks, but oriented todesktopsEEMBC EDN Embedded Benchmark Consortium,www.eembc.orgSuites of benchmarks: automotive, consumerelectronics, networking, office automation,telecommunicationsPCIRvon Neumann Architectureaddressmemorydata200CPU200ADD r5,r1,r3ADD r5,r1,r3Harvard archit
9、ectureaddressdata memoryprogram memorydataaddressdataPCCPUvon Neumann vs. HarvardHarvard cant use self-modifying code.Harvard allows two simultaneous memoryfetches.Most DSP use Harvard architecture forstreaming data:greater memory bandwidth;more predictable bandwidth.ARM vs. SHARCARM7 is von Neumann
10、 architectureWe will concentrate on ARM7ARM9 is Harvard architectureSHARC is modified Harvard architecture.On chip memory ( 1Gbit) evenly split betweenprogram memory (PM) and data memory (DM)Program memory can be used to store some data.Allows data to be fetched from both memory in paralleluP Perfor
11、manceWidth of data pathperformance ( Width of Data Path ) 2The most general categorization of processor performanceTypical data bus widths: 4, 8, 16, 32, 64, 128 bits wideWider data busses - greater data processing capabilityData bus width trade-off, the wider data path:Is more complex to designTake
12、s up more room on PC boardsGenerates greater amounts of energyRequires more costly memory designsIs not compatible with existing hardwareMore on data path widthData path width generally determines functionality4,8 bits - Appliances, modems, simple applications16 bits - Industrial controllers, automo
13、tive32 bits - Telecomm, laser printers, high-performance apps64 bits - PCs, UNIX workstations, games128, 256 bits (VLIW) - Next generationInternal and external data paths may differ in sizeNarrower memory is more economicalMC68000: 32-bit internal/16-bit externalMC68008: 32-bit internal/8-bit extern
14、al80C188: 16-bit internal/8-bit externalRemember: An 8-bit processor can do almost everything a 64-bitprocessor can do, it will just take longer to accomplishProcessor Micro-architectureOn-chip instruction/data cache, how big?PipelinesSuperscalar/VLIWTrade-off - high performance costs money, powerAd
15、dress bus designAddress bus width: 16 - 36 bitsMultiplexed, synchronous, asynchronousProcessor type: CISC, RISC, DSPWhat is the nature of the algorithm to implement?Control rich: CISCData rich: RISCData transforms and mathematical processing: DSPMore on address bus widthThe amount of externally acce
16、ssible memory is defined asthe Address Space of the processorCan vary from 1KB for simple microcontrollers to over 60 GBin high performance processorsSize of the address space doesnt mean that you have thatmuch memory, it only means that the capabilities exist todirectly access itProcessors with sma
17、ller address spaces can still manipulatelarger memory arrays with techniques such as PagingSpecial memory or I/O location used to swap in and outmemory pagesExample: An 8-bit Z80 processor with a 16-bit addressbus ( 64K) can address a 1Mbyte address space byswapping between one of 16, 64Kbyte, memor
18、y pagesSingle or Multiple processorsCombine CISC, RISC and DSP in a singledesignTight coupling or loose couplingArchitectureCode design, compiler capabilitiesDebug tool availabilitySystem simulation toolsIntegration of functionsMicroprocessor or microcontroller?Review:A microprocessor contains the b
19、asic CPU functionality, and moreA microcontroller combines the CPU core with peripheral devicesThe microprocessor is usually the leading edge of performanceLowest level of integrationHighest costHigher levels of integration implyLower system costsGreater reliabilityLess powerFasterHigher processor c
20、ostAs uP matures the core moves into the uC familiesCPU CoreRAMROMFLASHTimersWatchdogCoprocessorLCD ControllerDMACSSAP490B$100KNREFLASHPCI BusBridgeReal-timeClockCacheA/D ConverterSerial PortsEthernetParallel Ports主要内容嵌入式设计生命周期选择过程划分决策详细的硬件与软件设计嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程开发、调试环境与工具划分决策软件与硬件的双重性软件与硬件
21、的分离：基于开发成本和性能的决策新的硬件描述语言：HDLHandel-C协同设计过程Hardware/Software PartitioningDefinitionThe process of deciding, for each subsystem, whetherthe required functionality is more advantageouslyimplemented in hardware or softwareGoalTo achieve a partition that will give us the requiredperformance within the ov
22、erall system requirements (insize, weight, power, cost, etc.)This is a multivariate optimization problem thatwhen automated, is an NP-hard problemHW/SW Partitioning IssuesPartitioning into hardware and software affectsoverall system cost and performanceHardware implementationProvides higher performa
23、nce via hardwarespeeds and parallel execution of operationsIncurs additional expense of fabricating ASICsSoftware implementationMay run on high-performance processors at lowcost (due to high-volume production)Incurs high cost of developing and maintaining(complex) softwarePartitioning ApproachesStar
24、t with all functionality in software and moveportions into hardware which are time-critical andcan not be allocated to software(software-oriented partitioning)Start with all functionality in hardware and moveportions into software implementation(hardware-oriented partitioning)主要内容嵌入式设计生命周期选择过程划分决策详细
25、的硬件与软件设计嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程开发、调试环境与工具软硬件设计过程中的文档管理需求分析文档（产品定义阶段）总体方案设计（选择过程和软硬件划分）概要设计文档（软硬件初步设计）详细设计文档（软硬件详细设计）测试需求文档（模块测试及联调准备）系统测试报告（测试小组）使用说明文档/源程序注释总体方案设计项目概述（来自需求分析文档）功能与指标描述（来自需求分析文档）系统外部接口描述系统软硬件设计框架（选择过程和划分决策）软硬件模块化设计概要功能、接口时间与进度安排（甘特图）产品成本估算研制经费需求甘特图任务技术方案设计系统软件构建系统联调、设计验证BSP及设备驱动程
26、序春节产品现场测试原理图及PCB设计PCB制板及硬件调试设计完善IP Core及FPGA设计与仿真时间2002/12/12003/1/12003/2/12003/3/12003/4/12003/5/1图4 项目研制进度与计划安排模块化设计功能描述接口描述：硬件接口与软件参数设计流图自然语言流程框图原理框图状态流图UML：统一建模描述语言状态流图软硬件统一描述方式Memo ButtonTurn on theWarningReset WarningTurnoff thewarningMessagecounter = 24Check thenumber ofmessagesMessage = 1-
27、23,24-29Generatememory addressand recordmessage & incmessage counterMemoryPage is fullMessageCounter = 30Delete the firstmessage anddecrementHang UpmessagecounterState Diagram of Recording a Message主要内容嵌入式设计生命周期选择过程划分决策详细的硬件与软件设计嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程开发、调试环境与工具嵌入式软件开发环境SourceListingSourceListin
28、gCreate UserLibrary(optional)LibrarianC or C+Source FileC or C+CompilerAssemblySource FileAssemblerRelocatableObjectModuleUserLibraryIncludeFilesLibraryDirectoryListingLinkerCommandFileDeviceProgrammerAbsoluteRelocatableObjectLinkerObjectTargetModuleModuleDevelopmentSystemLink MapDebugging ToolsetIn
29、struction Set Simulator (ISS)Debug MonitorROM EmulatorLogic AnalyzerIn-Circuit Emulator (ICE)Joint Test Action Group (JTAG)Debugging embedded systemsChallenges:target system may be hard to observe;target may be hard to control;may be hard to generate realistic inputs;setup sequence may be complex.In
30、struction Level SimulatorHost based software that simulates thefunctionality and instruction set of the targetprocessorTwo typesFunctionality-accurateImplements only instruction setCycle-accurateMaintain cycle-by-cycle accuracy of processor, including cache,pipeline, and memory behaviorUseful in ear
31、ly stage of the projectDisadvantage:No simulation of peripheralsRemote DebuggerFront-end runs on host computer andprovides user interfaceBackend runs on target processor andcommunicates with the front-end overcommunication linkBackend is known as debug monitor andprovides low level control of target
32、processorDebug monitorA monitor program residing on the target ROMprovides basic debugger functionsRead register xModify register yRead n bytes of memory starting at addressModify data at addressRun to breakpointSingle stepLoad codeDebugger should have minimal footprint inmemory.User program must be
33、 careful not to destroydebugger programDebug monitor (Contd.)HOST-BASED DEBUGGER PROGRAM- Knowledge of source files- Knowledge of object filesSYSTEM ROMCODE PARTITION Symbol Table Cross reference filesPower onreset codeSerial Port0xFFFFF32ISRDebugKernel21ApplicationProgramSoftware0 1debug trapvector
34、SERIAL COMM LINKSerial PortInt. Vector0x000000Debug monitors: AdvantagesLow cost: $0 to 200 channels, 1GHz data ratesCan observe entire digital system at the sametimeCan be used in conjunction with instrumentedcode for real time measurements in cachedprocessorsLogic Analyzer: DisadvantagesCan be ver
35、y expensiveStrictly passive, cannot provide control ofprocessorComplexNot well-integrated into software designenvironmentMust combine with other tools for completesolutionCached processors cannot be observedCode must be instrumented if cache is not visibleIn-circuit emulators (ICE)An ICE provides an
36、 integration of the mostimportant functions required to debugembedded systemsMicroprocessor run Control (Debug monitor)Memory substitution (ROM Emulator)Real Time Trace (Logic Analyzer)A microprocessor in-circuit emulator is aspecially-instrumented microprocessor.nginrA typical engineer with emulato
37、rEmulatorHost ComputerTypical eeeTarget systemICE (Contd.)Host computer runs emulator control software- Provides run control- Displays real time trace at source level- Loads overlay memory with object code- High-speed link to emulation chassisProbe head contain emulation microprocessor- Substitutes
38、for, or disables target microprocessor- Contains run control circuitry and cable buffers- May contain memory mapping hardwareTarget systemMain chassis- Contains emulation ( overlay memory )- Trace analysis hardware and trace memory- Performance analysis hardware (- Power supply- Control and communic
39、ationsICE (Contd.)Run controlSimilar to the functionality of a software debug kernelPeek/poke memoryModify registersSingle stepSet breakpointsDisassemble memory codeDownload codeICE ( contd. )Overlay memorySimilar to functionality of ROM emulatorProvides overlay ( substitution ) memory for target sy
40、stemmemoryEntire memory space can be “mapped” to provide memoryregions in anywhere in the address space of targetprocessorEmulation memory interspersed with target systemmemoryEmulation memory can be assigned special attributesROM ( no writes allowed )Guarded ( break on write )Code space or data spa
41、ceShared memory ( simulated I/O )ICE AdvantagesPremier tool for embedded system hw/sw integrationProvides all the functionality needed for connectivity,observation and control of an embedded systemControl of the microprocessor is guaranteed,independent of the state of target system hardwareOverlay m
42、emory substitutes for the target systemROM to permit trace of code executionTraces program flowFilter out extraneous bus activity ( pre-fetches )Special circuitry can display cache activityTight integration through single user interface on hostCan provide very unique and valuable measurementsICE: Di
43、sadvantagesNot always most cost-effective solutionCan be extremely expensive ( $20K )Costly to equip a team of designersNew emulator often required for new processor or upgradeViewed as a complex and fragile instrumentAvailability usually lags early siliconCannot easily track microcontroller variant
44、sConnectivity to surface-mounted processors is very difficult,and the problem is getting worseViewing cached program activity can be very difficult ( or, atworst ) impossibleNot the tool of choice for code design at the upper levels ofabstractionJoint Test Action Group (JTAG)Originally developed as
45、a board test methodologyto replace “bed of nails” testersPC boards tested on complex machines with densearray of point contacts (bed of nails) to connect toevery node on the boardNode is a shared interconnection between boardcomponentsLink outputs of all digital devices on PC boardwith individual bi
46、ts of one long shift registerCan observe whether any circuit node is stuckhigh, low, shorted or disconnectedJTAG LoopEach JTAG cell “sniffs” the state of the corresponding output bit of the ICJTAG ConnectorJTAG bit stream inJTAG bit stream outPC BoardBit stream forms one long shift-registerJTAG can
47、be a debug protocolLink all the internal registers and other importantcircuit blocks in a JTAG loopProvide capability to drive output as well as sniffitAdd internal debug registers accessible via JTAGCan provide a low-cost standard debug interface,independent of chip variationsGreat for silicon vend
48、ors and end usersOne low-cost ( $100 tool ) supports any JTAG-compatible deviceAddrBusInterfaceProcessor CoreJTAG-based debug kernelClock inJTAG inProgram Counter - PCRegister R1Register R2Register RnJTAG outStatus Bus InterfaceJTAG ControlState MachineProcessor Core“SPECIAL” REGISTER SETData Bus In
49、terfaceMore on JTAGDe-facto standard for on-chip debugVery cost effectiveCan be re-programmed to support multipleprocessor familiesTypically priced under $1000Debug capability is defined by features of debug coreCan be slowBus cycles must be constructed by laboriouslyshifting every bitLoops can be extremely long ( 10,000 bits )Method of choice for processors in ASIC coresLends itself to RISC processors because core logictends to be simpler than CISCDesign-intensive as JTAG loops must be hand crafted有时间的话再看一个Project例子请参照例子准备Project交流课件
