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1、Chapter 2: Computer-System StructuresnComputer System OperationnI/O StructurenStorage Structure nStorage Hierarchy nHardware Protection nGeneral System ArchitectureUniprocessor Computer-System ArchitecturecontrollerControllernA device controller is a part of a computer system that makes sense of the
2、 signals going to, and coming from the CPU processor. Each device controller is in charge of a particular device type. nDevice controllers use binary and digital codes. Each device controller has a local buffer and a command register. I/O is from the device to local buffer of controller. nI/O device
3、s and the CPU can execute concurrently. Device controllers communicate with the CPU by causing an interrupt. Functions of device controllersnReceiving and understanding the commands of CPUnimplementing the data exchange between CPU and devices (format conversion)nRecording the status of device to be
4、 queried by CPU (status register)nIdentifying the address of each deviceCommon Functions of InterruptsnInterrupts transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines. 通常中断通过中断向量把控制传给中断服务程序nInterrupt arch
5、itecture must save the address of the interrupted instruction. nIncoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt.nA trap is a software-generated interrupt caused either by an error or a user request.nAn operating system is interrupt driven.Inter
6、rupt HandlingnThe operating system preserves the state of the CPU by storing registers and the program counter. nDetermines which type of interrupt has occurred:npolling nvectored interrupt system nSeparate segments of code determine what action should be taken for each type of interrupt Interrupt T
7、ime Line For a Single Process Doing Output (P21)Chapter 2: Computer-System StructuresnComputer System OperationnI/O StructurenStorage Structure nStorage Hierarchy nHardware Protection nGeneral System ArchitectureI/O Structure1. No channel (IOP):npollingCPU-OrientedCPURAMCCCCDisk DrivePrinterDeviceSy
8、stem BusI/O Structure2. channel (IOP):Memory-OrientedC1IOP1CPURAMIOP2C2C3C4Device1Device2Device3Device4Device5Device6Device7How to output the data in RAM ?nConstruct a channel programnSubmit the channel program to the corresponding IOP via RAMnThe IOP executes the channel programnThe IOP notifies CP
9、U by causing an interrupt upon completion A channel program is a sequence of I/O instructions executed by the input/output channel processor (IOP). The channel program consists of one or more channel command words. Two I/O MethodsSynchronousAsynchronousSynchronous I/OnAfter I/O starts, control retur
10、ns to user program only upon I/O completion. nwait instruction idles the CPU until the next interruptnwait loop (contention for memory access). nAt most one I/O request is outstanding at a time, no simultaneous I/O processing. Asynchronous I/OnAfter I/O starts, control returns to user program, witho
11、ut waiting for I/O completion. nSystem call request to the operating system to allow user to wait for I/O completion. nDevice-status table contains entry for each I/O device indicating its type, address, and state. nOperating system indexes into I/O device table to determine device status and to mod
12、ify table entry to include interrupt.nThe main advantage of asynchronous I/O is increased system efficiency.Device-Status TableI/O StructurenProgrammed input/output (PIO) is a method of transferring data between the CPU and a peripheral. In general, programmed I/O happens when software running on th
13、e CPU uses instructions that access I/O address space to perform data transfers to or from an I/O device.nWith Direct Memory Access (DMA) , the CPU would initiate the transfer, do other operations while the transfer is in progress, and receive an interrupt from the DMA controller once the operation
14、has been done. Direct Memory Access (DMA) StructurenUsed for high-speed I/O devices able to transmit information at close to memory speeds.nDevice controller transfers blocks of data from buffer storage directly to main memory without CPU intervention.nOnly one interrupt is generated per block, rath
15、er than the one interrupt per byte.Chapter 2: Computer-System StructuresnComputer System OperationnI/O StructurenStorage Structure nStorage Hierarchy nHardware Protection nGeneral System ArchitectureStorage StructurenMain memory only large storage media that the CPU can access directly. nSecondary s
16、torage extension of main memory that provides large nonvolatile storage capacity.nMagnetic disks rigid metal or glass platters covered with magnetic recording materialnDisk surface is logically divided into tracks, which are subdivided into sectors.nThe disk controller determines the logical interac
17、tion between the device and the computer. Moving-Head Disk MechanismnPositioning time (random-access time)nseek time nrotational latencyntransfer timenTo decrease mechanical delays, i.e., the seek time and the rotational latency Disk Scheduling AlgorithmChapter 2: Computer-System StructuresnComputer
18、 System OperationnI/O StructurenStorage Structure nStorage Hierarchy nHardware Protection nGeneral System ArchitectureStorage HierarchynStorage systems organized in hierarchy.nSpeed ncost nvolatility nCaching copying information into faster storage system; main memory can be viewed as a fast cache f
19、or secondary storage.Storage-Device Hierarchy寄存器寄存器缓存缓存主存储器主存储器电子盘电子盘磁盘磁盘光盘光盘磁带磁带Chapter 2: Computer-System StructuresnComputer System OperationnI/O StructurenStorage Structure nStorage Hierarchy nHardware Protection nGeneral System ArchitectureHardware ProtectionnDual-Mode OperationnI/O Protectionn
20、Memory ProtectionnCPU ProtectionDual-Mode OperationnSharing system resources requires operating system to ensure that an incorrect program cannot cause other programs to execute incorrectly.nProvide hardware support to differentiate between at least two modes of operations. 至少在两个运行模式之间提供硬件支持至少在两个运行模
21、式之间提供硬件支持1.User mode execution done on behalf of a user.2.Monitor mode (also supervisor mode or system mode) execution done on behalf of operating system. usernWhen an interrupt or fault occurs hardware switches to monitor mode.Dual-Mode Operation (Cont.)nMode bit added to computer hardware (PSW) to
22、 indicate the current mode: monitor (0) or user (1). Privileged instructions can be issued only in monitor mode. 特权指令特权指令只能在管态下执行只能在管态下执行 monitorInterrupt/faultset user modeI/O ProtectionnPrivileged instructionsnAll I/O instructions are privileged instructions.nEnable/disable interruptsnModify addre
23、ss registersnSet PSWnMust ensure that a user program could never gain control of the computer in monitor mode.Memory ProtectionnMust provide memory protection at least for the interrupt vector and the interrupt service routines.nIn order to have memory protection, add two registers that determine th
24、e range of legal addresses a program may access:nbase register holds the smallest legal physical memory address.nlimit register contains the size of the rangenMemory outside the defined range is protected.A Base And A limit Register Define A Logical Address SpaceHardware ProtectionnWhen executing in
25、 monitor mode, the operating system has unrestricted access to both monitor and users memory.nThe load instructions for the base and limit registers are privileged instructions. CPU ProtectionnTimer interrupts computer after specified period to ensure operating system maintains control. nTimer is de
26、cremented every clock tick.nWhen timer reaches the value 0, an interrupt occurs. nTimer commonly used to implement time sharing.nTimer also used to compute the current time. Load-timer is a privileged instruction.Chapter 2: Computer-System StructuresnComputer System OperationnI/O StructurenStorage S
27、tructure nStorage Hierarchy nHardware Protection nGeneral System ArchitectureGeneral-System ArchitecturenGiven the I/O instructions are privileged, how does the user program perform I/O? nSystem call the method used by a process to request action by the operating system.nUsually takes the form of a
28、trap to a specific location in the interrupt vector.nControl passes through the interrupt vector to a service routine in the OS, and the mode bit is set to monitor mode. nThe monitor verifies that the parameters are correct and legal, executes the request, and returns control to the instruction following the system call. Use of A System Call to Perform I/OHomeworknP41-P42 n2.2n2.3n2.5n2.9
