先进芯片封装知识介绍

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1、AdvancedPackagingTechAdvancedPackagingTech.OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage.PackageDevelopmentTrend.SOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend.CSPFamilyMemoryCardSiPModulePackageDevelopmentTrend.3DPackage3DPackage.3DPackageIntroductionetCSPStackFunctionalIntegratio

2、nHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP3S-CSPS-etCSPetCSP+S-CSPPS-fcCSP+SCSPPoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP5SCSPSS-SCSP(pa

3、ste)UltrathinStackD2D3D4D2D2D3D4D2PoPQFN4SS-SCSP.StackedDieTopdieBottomdieFOWmaterilWire.TSVTSV(ThroughSiliconVia)Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.A3Dpackage(Syst

4、eminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace.Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips.Ins

5、omenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV.WhatsPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.PoP.PoPPS-vfBGAPS-etCSPL

6、owLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology.PoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflip

7、chip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkorsTMVPoPTop viewBottom viewThrough Mold Via.PoPBallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseMtlThermaleffectProcessFlow

8、ofTMVPoP.Digital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP.EasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPfor

9、matIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?PiP.MaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISM

10、PiPCoreTechnologyPiP.MemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiPW/BPiPandFCPiP.WLCSP&FlipChipPackage.WLCSPWhatisWLCSP?WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%incre

11、asedcomparedtodiesize).WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.WLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soitha

12、swidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSPsdisadvantageBecauseofthediesizea

13、ndpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.RDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafersactivesurfacetore-routethebondpads.Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).WLCSPProces

14、sFlowofWLCSP.WLCSPProcessFlowofWLCSP.FlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMult

15、iPackageFlipChip).Bump.BumpDevelopment.BumpDevelopment.BumpDevelopment.C4FlipChipWhatsC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,gold.C4FlipChipBGAMainFeaturesBallPitch:0.4mm-1.27mmPackagesize:upto55mmx55mmSubstratelayer:4-16LayersB

16、allCount:upto2912TargetMarket:CPU、FPGA、Processor、 Chipset、Memory、Router、 Switches、 andDSPetc.MainBenefitsReducedSignalInductanceReducedPower/GroundInductanceHigherSignalDensityDieShrink&ReducedPackageFootprintHighSpeedandHighthermalsupport.C2FlipChipWhatsC2FlipChip?C2is:ChipConnectionChipisconnectedtosubstratebycopperpostBumpmaterialtype:copperpostwithsolderplatingSiliconDieCopperpostSolder.C2FlipChipProcessFlowofC2.C2FlipChipComparison:C2VsC4Insomecases,C2canreplaceC4orwirebondingpackage.Thanks!.

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